JP2019526932A5 - - Google Patents
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- Publication number
- JP2019526932A5 JP2019526932A5 JP2019509513A JP2019509513A JP2019526932A5 JP 2019526932 A5 JP2019526932 A5 JP 2019526932A5 JP 2019509513 A JP2019509513 A JP 2019509513A JP 2019509513 A JP2019509513 A JP 2019509513A JP 2019526932 A5 JP2019526932 A5 JP 2019526932A5
- Authority
- JP
- Japan
- Prior art keywords
- trench
- integrated circuit
- substrate
- conductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims 28
- 239000004020 conductor Substances 0.000 claims 20
- 238000000034 method Methods 0.000 claims 13
- 230000015556 catabolic process Effects 0.000 claims 6
- 230000005684 electric field Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 238000009271 trench method Methods 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021133052A JP7293293B2 (ja) | 2016-08-16 | 2021-08-18 | 高電圧隔離のためのデュアルディープトレンチ |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/238,198 | 2016-08-16 | ||
| US15/238,198 US9786665B1 (en) | 2016-08-16 | 2016-08-16 | Dual deep trenches for high voltage isolation |
| PCT/US2017/047151 WO2018035229A2 (en) | 2016-08-16 | 2017-08-16 | Dual deep trenches for high voltage isolation |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021133052A Division JP7293293B2 (ja) | 2016-08-16 | 2021-08-18 | 高電圧隔離のためのデュアルディープトレンチ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019526932A JP2019526932A (ja) | 2019-09-19 |
| JP2019526932A5 true JP2019526932A5 (enExample) | 2020-09-24 |
| JP6936454B2 JP6936454B2 (ja) | 2021-09-15 |
Family
ID=59982153
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019509513A Active JP6936454B2 (ja) | 2016-08-16 | 2017-08-16 | 高電圧隔離のためのデュアルディープトレンチ |
| JP2021133052A Active JP7293293B2 (ja) | 2016-08-16 | 2021-08-18 | 高電圧隔離のためのデュアルディープトレンチ |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021133052A Active JP7293293B2 (ja) | 2016-08-16 | 2021-08-18 | 高電圧隔離のためのデュアルディープトレンチ |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9786665B1 (enExample) |
| EP (1) | EP3501040B1 (enExample) |
| JP (2) | JP6936454B2 (enExample) |
| CN (1) | CN109564895B (enExample) |
| WO (1) | WO2018035229A2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9786665B1 (en) * | 2016-08-16 | 2017-10-10 | Texas Instruments Incorporated | Dual deep trenches for high voltage isolation |
| US10262997B2 (en) * | 2017-09-14 | 2019-04-16 | Vanguard International Semiconductor Corporation | High-voltage LDMOSFET devices having polysilicon trench-type guard rings |
| CN111341847B (zh) * | 2018-12-19 | 2023-03-28 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
| US10811543B2 (en) * | 2018-12-26 | 2020-10-20 | Texas Instruments Incorporated | Semiconductor device with deep trench isolation and trench capacitor |
| US11158750B2 (en) | 2019-07-03 | 2021-10-26 | Texas Instruments Incorporated | Superlattice photo detector |
| US11502036B2 (en) * | 2020-02-07 | 2022-11-15 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| DE112021006557B4 (de) | 2021-01-15 | 2025-02-20 | Rohm Co., Ltd. | Halbleitervorrichtungen |
| JP7724087B2 (ja) * | 2021-06-16 | 2025-08-15 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| JP7748832B2 (ja) * | 2021-08-26 | 2025-10-03 | ローム株式会社 | 半導体装置 |
| US12087813B2 (en) * | 2021-08-31 | 2024-09-10 | Texas Instruments Incorporated | Deep trench isolation with field oxide |
| US12159910B2 (en) * | 2022-02-15 | 2024-12-03 | Globalfoundries U.S. Inc. | Isolation regions for charge collection and removal |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4819052A (en) * | 1986-12-22 | 1989-04-04 | Texas Instruments Incorporated | Merged bipolar/CMOS technology using electrically active trench |
| JP3189743B2 (ja) * | 1997-06-26 | 2001-07-16 | 日本電気株式会社 | 半導体集積回路装置及びその製造方法 |
| US6316336B1 (en) * | 1999-03-01 | 2001-11-13 | Richard A. Blanchard | Method for forming buried layers with top-side contacts and the resulting structure |
| GB0507157D0 (en) | 2005-04-08 | 2005-05-18 | Ami Semiconductor Belgium Bvba | Double trench for isolation of semiconductor devices |
| JP2007201220A (ja) | 2006-01-27 | 2007-08-09 | Mitsubishi Electric Corp | 半導体装置 |
| JP2008034649A (ja) * | 2006-07-28 | 2008-02-14 | Sanyo Electric Co Ltd | 半導体装置 |
| EP2006900B1 (en) * | 2007-05-25 | 2020-11-18 | Semiconductor Components Industries, LLC | Deep trench isolation for power semiconductors |
| US7982282B2 (en) * | 2008-04-25 | 2011-07-19 | Freescale Semiconductor, Inc. | High efficiency amplifier with reduced parasitic capacitance |
| JP2010062377A (ja) * | 2008-09-04 | 2010-03-18 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
| US20100181639A1 (en) * | 2009-01-19 | 2010-07-22 | Vanguard International Semiconductor Corporation | Semiconductor devices and fabrication methods thereof |
| JP2011171602A (ja) | 2010-02-19 | 2011-09-01 | Oki Semiconductor Co Ltd | 半導体装置およびその製造方法 |
| EP2498280B1 (en) * | 2011-03-11 | 2020-04-29 | Soitec | DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof |
| FR2991502B1 (fr) * | 2012-05-29 | 2014-07-11 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre ayant des tranchees d'isolation avec des profondeurs distinctes |
| US9159791B2 (en) * | 2012-06-06 | 2015-10-13 | United Microelectronics Corp. | Semiconductor device comprising a conductive region |
| US9343526B2 (en) * | 2013-03-13 | 2016-05-17 | Freescale Semiconductor, Inc. | Deep trench isolation |
| KR102057340B1 (ko) * | 2013-03-29 | 2019-12-19 | 매그나칩 반도체 유한회사 | 반도체 소자 및 그 제조방법 |
| CN104701172B (zh) * | 2013-12-05 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Vdmos场效应晶体管及其形成方法 |
| US9252213B2 (en) * | 2013-12-19 | 2016-02-02 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with a buried N layer and methods for producing such integrated circuits |
| FR3021457B1 (fr) * | 2014-05-21 | 2017-10-13 | St Microelectronics Rousset | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et condensateur de decouplage associe |
| JP6238234B2 (ja) | 2014-06-03 | 2017-11-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US9660074B2 (en) | 2014-08-07 | 2017-05-23 | Texas Instruments Incorporated | Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers |
| US9401410B2 (en) * | 2014-11-26 | 2016-07-26 | Texas Instruments Incorporated | Poly sandwich for deep trench fill |
| US9673084B2 (en) | 2014-12-04 | 2017-06-06 | Globalfoundries Singapore Pte. Ltd. | Isolation scheme for high voltage device |
| JP6695188B2 (ja) * | 2016-03-29 | 2020-05-20 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US9786665B1 (en) * | 2016-08-16 | 2017-10-10 | Texas Instruments Incorporated | Dual deep trenches for high voltage isolation |
-
2016
- 2016-08-16 US US15/238,198 patent/US9786665B1/en active Active
-
2017
- 2017-08-16 WO PCT/US2017/047151 patent/WO2018035229A2/en not_active Ceased
- 2017-08-16 JP JP2019509513A patent/JP6936454B2/ja active Active
- 2017-08-16 CN CN201780049630.XA patent/CN109564895B/zh active Active
- 2017-08-16 EP EP17842059.2A patent/EP3501040B1/en active Active
- 2017-08-21 US US15/681,466 patent/US10580775B2/en active Active
-
2021
- 2021-08-18 JP JP2021133052A patent/JP7293293B2/ja active Active
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