CN105632931A - 半导体器件的制造方法及半导体器件 - Google Patents

半导体器件的制造方法及半导体器件 Download PDF

Info

Publication number
CN105632931A
CN105632931A CN201410614306.6A CN201410614306A CN105632931A CN 105632931 A CN105632931 A CN 105632931A CN 201410614306 A CN201410614306 A CN 201410614306A CN 105632931 A CN105632931 A CN 105632931A
Authority
CN
China
Prior art keywords
semiconductor device
conductivity type
epitaxial layer
columns
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410614306.6A
Other languages
English (en)
Other versions
CN105632931B (zh
Inventor
张帅
李连杰
陈忠浩
韩峰
吴健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN201410614306.6A priority Critical patent/CN105632931B/zh
Priority to US14/586,453 priority patent/US20160126307A1/en
Publication of CN105632931A publication Critical patent/CN105632931A/zh
Priority to US16/855,253 priority patent/US11201211B2/en
Application granted granted Critical
Publication of CN105632931B publication Critical patent/CN105632931B/zh
Priority to US17/454,168 priority patent/US20220069074A1/en
Priority to US18/448,013 priority patent/US20230387196A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)

Abstract

本发明公开了一种半导体器件的制造方法及半导体器件，该半导体器件的制造方法包括：在具有多层结构的半导体衬底上形成第一导电类型体区，并在所述第一导电类型体区上形成沟槽；通过自对准的方式向所述沟槽底部进行离子注入操作，形成第一导电类型柱；向所述沟槽中填入填充物填充所述沟槽。本发明通过自对准的方式向沟槽底部进行离子注入操作形成P柱或N柱，并与P柱或N柱相对应的外延层形成超级结结构，因此，不仅半导体器件的面积更小并且性能优异，同时还可以集成于平面工艺。

Description

半导体器件的制造方法及半导体器件
技术领域
本发明涉及半导体领域，具体来说，涉及一种半导体器件的制造方法及半导体器件。
背景技术
半导体器件的几何结构尺寸持续显著缩小。现今的制造工艺所制造的器件通常具有小于65nm的部件尺寸。然而，在持续满足器件要求的同时，半导体器件的性能不兼容的问题也接踵而至，比如，当需要一种尺寸很小的半导体器件时，为了达到预期的尺寸大小往往在其性能方面并不会很好。
此外，如今对于半导体器件的应用更加灵活多变，因此半导体技术的局限性也将凸显出来，LDMOS可以集成于平面，但是其具有较大的尺寸并且性能不好，具有较高的比导通电阻；DMOS具有良好的性能，但是其并不能集成于平面。
因此，尽管现今的方法和器件对其目的而言在多方面都是令人满意的和有效的，但仍需要对半导体技术进行改进使其性能更加均衡兼容。
发明内容
针对相关技术中的问题，本发明提出一种半导体器件的制造方法及半导体器件，能够具有小巧的尺寸优良的性能并且可以集成于平面，性能均衡且兼容。
本发明的技术方案是这样实现的：
根据本发明的一个方面，提供了一种半导体器件的制造方法。
该方法包括：
在具有多层结构的半导体衬底上形成第一导电类型体区，并在第一导电类型体区上形成沟槽；
通过自对准的方式向沟槽底部进行离子注入操作，形成第一导电类型柱；
向沟槽中填入填充物填充沟槽。
此外，在向沟槽中填入填充物之前，在沟槽的表面形成氧化物。
优选的，多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
并且，第一导电类型柱形成于栅极下方。
优选的，填充物为重掺杂的多晶硅或金属。
优选的，进行离子注入的条件包括以下至少之一：
注入能量为30keV至1800keV、注入剂量为1E12至2E13原子数每立方厘米、所述第二导电类型外延层的厚度为1至10um。
根据本发明的另一方面，提供了一种半导体器件，半导体器件包括终端区，以及与终端区分别相连的隔离区和核心区，其特征在于，核心区包括：具有多层结构的半导体衬底及第一导电类型柱，其中，第一导电类型柱是上述的半导体器件的制造方法中的第一导电类型柱。
优选的，多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
优选的，形成第一导电类型柱的条件包括以下至少之一：
进行离子注入的能量为30keV至1800keV、注入剂量为1E12至2E13原子数每立方厘米、第二导电类型外延层的厚度为1至10um。
此外，第一导电类型柱形成于栅极下方。
本发明通过自对准的方式向沟槽底部进行离子注入操作形成第一导电类型柱，并与第一导电类型柱相对应的第二导电类型外延层形成超级结结构，因此，不仅半导体器件的面积更小并且性能优异，同时还可以集成于平面工艺。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是传统工艺生产的LDMOS示意图；
图2是传统工艺生产的DMOS示意图；
图3是根据本发明实施例的半导体器件的制造方法的流程图；
图4-图9示出的是与图3方法的一个或多个步骤相应的半导体器件的实施例的截面图；
图10是根据本发明实施例的一具体半导体器件的示意图；
图11及图12是根据本发明实施例半导体器件的电场分布模拟图和线状示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
在实现本发明的过程中，发明人发现，如图1所示的传统工艺生产的LDMOS半导体器件，其栅极、漏极、源极，均在同一位面因此可以集成于平面，但是对其尺寸会有较大的限制并且性能不够好；如图2所示的传统工艺生产的DMOS半导体器件性能比较优异，但是其P柱是传统工艺的柱体植入形成，并且由于其栅极、源极、漏极，处于不同位面因此，不能集成于平面，此外，该DMOS还不可以与低压设备集成。
根据本发明的实施例，提供了一种半导体器件的制造方法。
如图3所示，根据本发明实施例的半导体的制造方法包括：
步骤S301，在具有多层结构的半导体衬底上形成第一导电类型体区，并在第一导电类型体区上形成沟槽；
步骤S303，通过自对准的方式向沟槽底部进行离子注入操作，形成第一导电类型柱；
步骤S305，向沟槽中填入填充物填充沟槽。
此外，在步骤S305，向沟槽中填入填充物之前，还需在沟槽的表面形成氧化物。
优选的，多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
优选的，第一导电类型柱形成于栅极下方。
优选的，填充物为重掺杂的多晶硅或金属。
优选的，进行离子注入的条件包括以下至少之一：
注入能量为30keV至1800keV、注入剂量为1E12至2E13原子数每立方厘米、所述第二导电类型外延层的厚度为1至10um。
当形成第一导电类型柱后，则在本发明的半导体结构中，第一导电类型柱将与第二导电类型外延层形成超级结结构(P柱与N型外延层形成超级结；N柱与P型外延层形成超级结)，因此，不仅半导体器件的面积更小并且性能优异，同时还可以集成于平面工艺。
在一个具体的实施例中，以形成P柱的过程为例，如图4-图9所示。
首先，请参照图4，提供一个具有多层结构的半导体衬底，该衬底包括：P型衬底、N型埋层、N型外延层。继续参照图5，在N型外延层上形成P型体区。参照图6，在形成的P型体区上通过蚀刻工艺形成沟槽。进而参照图7，在P型体区上形成沟槽后，通过自对准的方式向沟槽底部进行离子注入操作注入硼离子，形成P柱，需要注意的是，注入的材料是可以根据对半导体材料进行自由选择或组合的，比如形成P柱的离子材料还可以为磷等其他适当材料。在形成P柱时，其离子注入的条件为：
注入次数：约为(外延层材料厚度)/1um即，外延层厚度每1um注入一次；
注入能量：30keV-1800keV；
注入剂量：1E12-5E13atom/cm3；
外延层的厚度：1-10um,电压应用范围20-200V；
外延层的电阻率：0.1-1Ω.cm。
此时的P柱由于采取的工艺不同于传统的物理植入工艺，在进行离子注入过程中可以添加适当的、所需的各种材料来满足对半导体器件的性能的需求，在形成P柱后，该P柱与P柱相对应的N外延层形成超级结结构，并且器件漏极通过N型埋层在表面形成电极，因此，不仅半导体器件的面积更小并且性能优异，同时还可以集成于平面工艺。由于该方法对空间的限制较小因此可以用于生产微小型的半导体器件，并且不会影响其性能。在形成P柱后，继续参照图8，在沟槽的表面形成一层栅氧化物，之后，参照图9，再向沟槽内填充重掺杂的多晶硅或金属材料对沟槽进行填充，这时所生产的半导体器件就可以应用于其他后续的半导体器件的再加工或其他半导体技术。
如图10所示为根据上述半导体器件的制造方法的实施例所制造出的半导体器件的具体实物的示意图。
根据本发明的实施例还提供了一种半导体器件，该半导体器件包括：
终端区，以及与终端区分别相连的隔离区和核心区，其特征在于，核心区包括：具有多层结构的半导体衬底及第一导电类型柱，其中，第一导电类型柱是上述的半导体器件的制造方法中的第一导电类型柱。
优选的，多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
此外，第一导电类型柱形成于栅极下方。
以具有P柱的半导体器件为例进行说明，请参照图10，该半导体器件包括：隔离区、终端区以及核心区。
其中，终端区分别与隔离区及核心区相连，并且这三个区共用一个具有多层结构的半导体衬底，该多层结构的半导体衬底包括：P型衬底、N型埋层、N型外延层。
其中，隔离区中还包括P型沉阱。终端区中包括上述制造方法中形成的P柱、N型沉阱，且该N型沉阱可以由多晶硅和/或金属和/或重掺杂的N型硅组成。
核心区包括处于栅极下方的经重掺杂的多晶硅或金属填充的沟槽，在沟槽下方是上述制造方法中形成的P柱。
通过本发明制造的半导体器件的超级结结构由P柱及N型外延层构成，在如图10所示的半导体器件中，其电流方向为：N型沉阱—N型埋层—N型漂移区—经过电路到N+。本发明的超级结结构物质组成分布更加均衡，经过软件模拟其电场分布如图11所示，线状分布如图12所示，从中可以看出，本发明的半导体器件，电荷更加平衡且比通电阻更低，因此其性能相比于传统工艺的半导体器件性能更加优异并且还可以与低压设备集成。
综上，借助于本发明的上述技术方案，本发明通过自对准的方式向沟槽底部进行离子注入操作形成P柱或N柱，从而代替传统物理工艺形成的P柱，并且通过该植入方式生产而成的半导体器件电荷更加平衡，比导通电阻低，性能优异，可以与低压设备集成，因此该半导体器件可以集成于平面，且体积小巧。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种半导体器件的制造方法，其特征在于，包括：
在具有多层结构的半导体衬底上形成第一导电类型体区，并在所述第一导电类型体区上形成沟槽；
通过自对准的方式向所述沟槽底部进行离子注入操作，形成第一导电类型柱；
向所述沟槽中填入填充物填充所述沟槽。
2.根据权利要求1所述的方法，其特征在于，在向所述沟槽中填入所述填充物之前，在所述沟槽的表面形成氧化物。
3.根据权利要求1所述的方法，其特征在于，所述多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
4.根据权利要求1所述的方法，其特征在于，所述第一导电类型柱形成于栅极下方。
5.根据权利要求1所述的方法，其特征在于，所述填充物为重掺杂的多晶硅或金属。
6.根据权利要求1所述的方法，其特征在于，进行离子注入的条件包括以下至少之一：
注入能量为30keV至1800keV、注入剂量为1E12至2E13原子数每立方厘米、所述第二导电类型外延层的厚度为1至10um。
7.一种半导体器件，所述半导体器件包括终端区，以及与所述终端区分别相连的隔离区和核心区，其特征在于，所述核心区包括：具有多层结构的半导体衬底及第一导电类型柱，其中，所述第一导电类型柱是如权利要求1-6任一项所述的半导体器件的制造方法中的第一导电类型柱。
8.根据权利要求7所述的半导体器件，其特征在于，所述多层结构的半导体衬底包括以下至少之一：
第一导电类型衬底、第二导电类型埋层、第二导电类型外延层。
9.根据权利要求7所述的半导体器件，其特征在于，形成所述第一导电类型柱的条件包括以下至少之一：
进行离子注入的能量为30keV至1800keV、注入剂量为1E12至2E13原子数每立方厘米、所述第二导电类型外延层的厚度为1至10um。
10.根据权利要求7所述的半导体器件，其特征在于，所述第一导电类型柱形成于栅极下方。
CN201410614306.6A 2014-11-04 2014-11-04 半导体器件的制造方法及半导体器件 Active CN105632931B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201410614306.6A CN105632931B (zh) 2014-11-04 2014-11-04 半导体器件的制造方法及半导体器件
US14/586,453 US20160126307A1 (en) 2014-11-04 2014-12-30 Semiconductor device having super junction structure, method for manufacturing the same and method for manufacturing super junction structure
US16/855,253 US11201211B2 (en) 2014-11-04 2020-04-22 Method of manufacturing a super junction structure and super junction structure
US17/454,168 US20220069074A1 (en) 2014-11-04 2021-11-09 Method of manufacturing a super junction structure and super junction structure
US18/448,013 US20230387196A1 (en) 2014-11-04 2023-08-10 Super junction structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410614306.6A CN105632931B (zh) 2014-11-04 2014-11-04 半导体器件的制造方法及半导体器件

Publications (2)

Publication Number Publication Date
CN105632931A true CN105632931A (zh) 2016-06-01
CN105632931B CN105632931B (zh) 2020-04-28

Family

ID=55853564

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410614306.6A Active CN105632931B (zh) 2014-11-04 2014-11-04 半导体器件的制造方法及半导体器件

Country Status (2)

Country Link
US (4) US20160126307A1 (zh)
CN (1) CN105632931B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108899282A (zh) * 2018-07-04 2018-11-27 张帅 带有电荷平衡结构的沟槽栅场效应晶体管及其制造方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法
CN116682734A (zh) * 2023-07-28 2023-09-01 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111697050B (zh) * 2019-03-13 2023-02-28 世界先进积体电路股份有限公司 半导体装置及其形成方法
CN111276540A (zh) * 2020-01-13 2020-06-12 上海瞻芯电子科技有限公司 沟槽栅功率mosfet及其制造方法
US20230040358A1 (en) * 2021-08-06 2023-02-09 Applied Materials, Inc. MOSFET Gate Shielding Using an Angled Implant
CN115084236B (zh) * 2022-07-27 2022-11-22 上海瞻芯电子科技有限公司 沟槽栅功率mosfet及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2836242Y (zh) * 2005-10-14 2006-11-08 西安电子科技大学 可集成的高压vdmos晶体管结构
US20070013000A1 (en) * 2005-07-12 2007-01-18 Masaki Shiraishi Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter
CN103390545A (zh) * 2012-05-08 2013-11-13 上海华虹Nec电子有限公司 改善沟槽型nmos漏源击穿电压的方法及其结构
CN104103693A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种u形沟槽的功率器件及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1254799B (it) * 1992-02-18 1995-10-11 St Microelectronics Srl Transistore vdmos con migliorate caratteristiche di tenuta di tensione.
US6001678A (en) * 1995-03-14 1999-12-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
JP3303601B2 (ja) * 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
JP3397057B2 (ja) * 1996-11-01 2003-04-14 日産自動車株式会社 半導体装置
JP3938964B2 (ja) * 1997-02-10 2007-06-27 三菱電機株式会社 高耐圧半導体装置およびその製造方法
KR100275756B1 (ko) * 1998-08-27 2000-12-15 김덕중 트렌치 절연 게이트 바이폴라 트랜지스터
DE19913375B4 (de) * 1999-03-24 2009-03-26 Infineon Technologies Ag Verfahren zur Herstellung einer MOS-Transistorstruktur
US6291298B1 (en) * 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
JP4865166B2 (ja) * 2001-08-30 2012-02-01 新電元工業株式会社 トランジスタの製造方法、ダイオードの製造方法
EP1671374B1 (en) * 2003-10-08 2018-05-09 Toyota Jidosha Kabushiki Kaisha Insulated gate type semiconductor device and manufacturing method thereof
GB0419867D0 (en) * 2004-09-08 2004-10-13 Koninkl Philips Electronics Nv Semiconductor devices and methods of manufacture thereof
JP2007019146A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体素子
DE102006025218B4 (de) * 2006-05-29 2009-02-19 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben
JP4640439B2 (ja) * 2008-04-17 2011-03-02 株式会社デンソー 炭化珪素半導体装置
US20130307058A1 (en) * 2012-05-18 2013-11-21 Infineon Technologies Austria Ag Semiconductor Devices Including Superjunction Structure and Method of Manufacturing
JP2016062975A (ja) * 2014-09-16 2016-04-25 株式会社東芝 半導体装置およびその製造方法
DE102015116576B4 (de) * 2015-09-30 2021-11-25 Infineon Technologies Austria Ag Superjunction-Halbleitervorrichtung mit entgegengesetzt dotierten Halbleiterbereichen, die in Gräben ausgebildet sind, und Verfahren zur Herstellung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070013000A1 (en) * 2005-07-12 2007-01-18 Masaki Shiraishi Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter
CN2836242Y (zh) * 2005-10-14 2006-11-08 西安电子科技大学 可集成的高压vdmos晶体管结构
CN103390545A (zh) * 2012-05-08 2013-11-13 上海华虹Nec电子有限公司 改善沟槽型nmos漏源击穿电压的方法及其结构
CN104103693A (zh) * 2014-07-25 2014-10-15 苏州东微半导体有限公司 一种u形沟槽的功率器件及其制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108899282A (zh) * 2018-07-04 2018-11-27 张帅 带有电荷平衡结构的沟槽栅场效应晶体管及其制造方法
CN108899282B (zh) * 2018-07-04 2021-09-14 济南安海半导体有限公司 带有电荷平衡结构的沟槽栅场效应晶体管及其制造方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法
CN116682734A (zh) * 2023-07-28 2023-09-01 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法
CN116682734B (zh) * 2023-07-28 2023-10-13 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

Also Published As

Publication number Publication date
US20230387196A1 (en) 2023-11-30
US11201211B2 (en) 2021-12-14
US20160126307A1 (en) 2016-05-05
CN105632931B (zh) 2020-04-28
US20200251553A1 (en) 2020-08-06
US20220069074A1 (en) 2022-03-03

Similar Documents

Publication Publication Date Title
CN105632931A (zh) 半导体器件的制造方法及半导体器件
US8643108B2 (en) Buffered finFET device
CN102867846B (zh) 半导体器件
KR101279574B1 (ko) 고전압 반도체 소자 및 그 제조 방법
CN103811549B (zh) 横向mosfet
CN103515202B (zh) 半导体器件及半导体器件的制造方法
CN109166922A (zh) 一种沟槽型超结功率终端结构及其制备方法
JP2019521529A (ja) パワーデバイス及びその製造方法
CN107331706A (zh) 沟槽栅超结器件及其制造方法
CN104409334B (zh) 一种超结器件的制备方法
CN207587740U (zh) 晶体管及半导体器件
CN107785365B (zh) 集成有结型场效应晶体管的器件及其制造方法
CN107785367B (zh) 集成有耗尽型结型场效应晶体管的器件及其制造方法
CN103199018B (zh) 场阻断型半导体器件的制造方法和器件结构
CN105895520A (zh) 超结器件制备工艺
CN208225884U (zh) 晶体管及半导体器件
CN106463544A (zh) 具有复合沟槽和植入柱的半导体器件
JP2006521706A (ja) 超接合デバイス及びその製造方法
KR20160032654A (ko) 반도체 장치 및 그 제조 방법
CN110323138B (zh) 一种ldmos器件的制造方法
CN111463131A (zh) 超结半导体器件及其制造方法
CN104124276B (zh) 一种超级结器件及其制作方法
CN111223931A (zh) 沟槽mosfet及其制造方法
CN104821334A (zh) N型ldmos器件及工艺方法
CN114823532A (zh) 超级结器件的制造方法、超级结器件、芯片和电路

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant