JP2006521706A - 超接合デバイス及びその製造方法 - Google Patents
超接合デバイス及びその製造方法 Download PDFInfo
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- JP2006521706A JP2006521706A JP2006509288A JP2006509288A JP2006521706A JP 2006521706 A JP2006521706 A JP 2006521706A JP 2006509288 A JP2006509288 A JP 2006509288A JP 2006509288 A JP2006509288 A JP 2006509288A JP 2006521706 A JP2006521706 A JP 2006521706A
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- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000007943 implant Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000002513 implantation Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 32
- 229910052710 silicon Inorganic materials 0.000 description 32
- 239000010703 silicon Substances 0.000 description 32
- 230000015556 catabolic process Effects 0.000 description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009377 nuclear transmutation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Abstract
Description
したがって、図2に示されたようなデバイスの場合、ピッチ(隣接したトレンチの中心間の距離によって決まるセルとセルの間隔)を狭くすることが望ましい。
Claims (17)
- パワーデバイスを製造する方法であって、
半導体基板を準備するステップと、
前記半導体基板の空いている表面上に第1の導電型の第1の半導体層をエピタキシャル成長させるステップと、
前記第1の半導体層の空いている表面上に、前記半導体層の一部を露出させる複数の窓を含み、注入を阻止する能力を備えたマスクを形成するステップと、
前記注入窓の下にある前記第1の半導体層に複数の縦方向に隣接した第2の導電型の領域を形成するため、前記注入窓を介して一連の注入を実行するステップと、
前記第1の半導体層に前記第2の導電型の縦向き領域を形成するため、前記第2の導電型の前記領域を連結する拡散促進を適用するステップと、
前記第1の半導体層の上に前記第2の導電型のチャネル領域を形成するステップと、
前記チャネル領域によって複数のMOSゲート構造を形成するステップと、
各MOSゲート構造に隣接して前記第1の導電型の導電性領域を形成するステップと、
前記基板の空いている表面上に第1の電気的コンタクトを形成するステップと、
少なくとも前記第1の導電型の前記導電性領域と電気的に接触した第2の電気的コンタクトを形成するステップと、
を含み、
前記第2の導電型の前記縦向き領域が前記第1の半導体層と実質的に電荷がバランスするようにした、方法。 - 前記注入窓の幅が0.25〜2.0ミクロンである、請求項1記載の方法。
- 前記第2の導電型の前記縦向き領域の幅が5ミクロン未満である、請求項1記載の方法。
- 前記チャネル領域が前記第2の導電型のエピタキシャル半導体層を成長させることによって形成される、請求項1記載の方法。
- 前記チャネル領域が前記第2の導電型のドーパントを前記エピタキシャル半導体層へ注入することにより形成される、請求項1記載の方法。
- 前記第1の導電型の前記第1の半導体層上で前記第1の導電型の第2の半導体層をエピタキシャル成長させるステップと、
前記第2の半導体層の空いている表面上に、前記第2の半導体層の一部を露出させる複数の窓を含み、注入を阻止する能力を備えた第2のマスクを形成するステップと、
前記注入窓の下にあり前記第1の半導体層内の前記第2の導電型の前記縦向き領域の上にある前記第2の半導体層に、複数の縦方向に隣接した前記第2の導電型の領域を形成するため、前記第2のマスク内の前記注入窓を介して一連の注入を実行するステップと、
を更に含む、請求項1記載の方法。 - 前記注入窓の幅が0.25〜2.0ミクロンである、請求項6記載の方法。
- 前記第2の導電型の前記縦向き領域の幅が5ミクロン未満である、請求項6記載の方法。
- 前記チャネル領域が前記第2の導電型のエピタキシャル半導体層を成長させることによって形成される、請求項6記載の方法。
- 前記チャネル領域が前記第2の導電型のドーパントを前記第2の半導体層へ注入することにより形成される、請求項6記載の方法。
- 前記第1の導電型の前記導電性領域がソース領域である、請求項1記載の方法。
- 前記第1の電気的コンタクトがドレインコンタクトであり、前記第2の電気的コンタクトがソースコンタクトである、請求項1記載の方法。
- 前記半導体基板が第1の導電型である、請求項1記載の方法。
- 前記マスクが酸化物から構成される、請求項1記載の方法。
- 前記マスクがフォトレジストから構成される、請求項1記載の方法。
- 前記マスクが窒化物から構成される、請求項1記載の方法。
- 前記エピタキシャル半導体層の成長、前記マスクの形成、前記一連の注入の実行、及び前記拡散促進の適用が3回以上繰り返される、請求項1記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US45764003P | 2003-03-25 | 2003-03-25 | |
US10/808,049 US6969657B2 (en) | 2003-03-25 | 2004-03-24 | Superjunction device and method of manufacture therefor |
PCT/US2004/009164 WO2004088717A2 (en) | 2003-03-25 | 2004-03-25 | Superjunction device and method of manufacture therefore |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006521706A true JP2006521706A (ja) | 2006-09-21 |
Family
ID=33135062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006509288A Ceased JP2006521706A (ja) | 2003-03-25 | 2004-03-25 | 超接合デバイス及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6969657B2 (ja) |
JP (1) | JP2006521706A (ja) |
DE (1) | DE112004000495B4 (ja) |
WO (1) | WO2004088717A2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
JP2016076729A (ja) * | 2015-12-28 | 2016-05-12 | 株式会社東芝 | 半導体装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10346838A1 (de) * | 2002-10-08 | 2004-05-13 | International Rectifier Corp., El Segundo | Superjunction-Bauteil |
JP4907862B2 (ja) * | 2004-12-10 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
EP1696490A1 (en) * | 2005-02-25 | 2006-08-30 | STMicroelectronics S.r.l. | Charge compensation semiconductor device and relative manufacturing process |
DE102005009000B4 (de) * | 2005-02-28 | 2009-04-02 | Infineon Technologies Austria Ag | Vertikales Halbleiterbauelement vom Grabenstrukturtyp und Herstellungsverfahren |
JP2007027193A (ja) * | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | 半導体装置およびその製造方法、ならびに非絶縁型dc/dcコンバータ |
JP4744958B2 (ja) * | 2005-07-13 | 2011-08-10 | 株式会社東芝 | 半導体素子及びその製造方法 |
US20110068397A1 (en) * | 2009-09-24 | 2011-03-24 | Disney Donald R | Power devices and associated methods of manufacturing |
JP2012064706A (ja) * | 2010-09-15 | 2012-03-29 | Toshiba Corp | 双方向定電圧ダイオード |
DE102015116040A1 (de) | 2015-09-23 | 2017-03-23 | Infineon Technologies Austria Ag | Halbleiterbauelemente und ein Verfahren zum Bilden von Halbleiterbauelementen |
CN112909075A (zh) * | 2021-01-28 | 2021-06-04 | 滁州华瑞微电子科技有限公司 | 一种具有电荷平衡结构的沟槽mosfet及其制作方法 |
CN114759081B (zh) * | 2022-06-14 | 2022-11-04 | 绍兴中芯集成电路制造股份有限公司 | 半导体结构及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000040822A (ja) * | 1998-07-24 | 2000-02-08 | Fuji Electric Co Ltd | 超接合半導体素子およびその製造方法 |
JP2000183348A (ja) * | 1998-12-09 | 2000-06-30 | Stmicroelectronics Srl | Mosゲ―ト電力装置 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP2003324196A (ja) * | 2002-04-30 | 2003-11-14 | Nec Electronics Corp | 縦型mosfetとその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0772244B1 (en) * | 1995-11-06 | 2000-03-22 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | MOS technology power device with low output resistance and low capacity and related manufacturing process |
US6639276B2 (en) * | 2001-07-05 | 2003-10-28 | International Rectifier Corporation | Power MOSFET with ultra-deep base and reduced on resistance |
-
2004
- 2004-03-24 US US10/808,049 patent/US6969657B2/en not_active Expired - Lifetime
- 2004-03-25 DE DE112004000495T patent/DE112004000495B4/de not_active Expired - Fee Related
- 2004-03-25 JP JP2006509288A patent/JP2006521706A/ja not_active Ceased
- 2004-03-25 WO PCT/US2004/009164 patent/WO2004088717A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000040822A (ja) * | 1998-07-24 | 2000-02-08 | Fuji Electric Co Ltd | 超接合半導体素子およびその製造方法 |
JP2000183348A (ja) * | 1998-12-09 | 2000-06-30 | Stmicroelectronics Srl | Mosゲ―ト電力装置 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP2003324196A (ja) * | 2002-04-30 | 2003-11-14 | Nec Electronics Corp | 縦型mosfetとその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
JP2016076729A (ja) * | 2015-12-28 | 2016-05-12 | 株式会社東芝 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
DE112004000495B4 (de) | 2010-07-22 |
US6969657B2 (en) | 2005-11-29 |
WO2004088717A2 (en) | 2004-10-14 |
US20040224455A1 (en) | 2004-11-11 |
WO2004088717A3 (en) | 2005-06-16 |
DE112004000495T5 (de) | 2006-03-30 |
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