US20160126307A1 - Semiconductor device having super junction structure, method for manufacturing the same and method for manufacturing super junction structure - Google Patents

Semiconductor device having super junction structure, method for manufacturing the same and method for manufacturing super junction structure Download PDF

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US20160126307A1
US20160126307A1 US14/586,453 US201414586453A US2016126307A1 US 20160126307 A1 US20160126307 A1 US 20160126307A1 US 201414586453 A US201414586453 A US 201414586453A US 2016126307 A1 US2016126307 A1 US 2016126307A1
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present disclosure
conductivity type
layer
trenches
doped
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Shuai Zhang
Lian-Jie LI
Zhong-Hao CHEN
Feng Han
Jian Wu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, Zhong-hao, HAN, FENG, LI, Lian-jie, WU, JIAN, ZHANG, Shuai
Publication of US20160126307A1 publication Critical patent/US20160126307A1/en
Priority to US16/855,253 priority Critical patent/US11201211B2/en
Priority to US17/454,168 priority patent/US12040358B2/en
Priority to US18/448,013 priority patent/US20230387196A1/en
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Definitions

  • a super junction MOSFET features higher breakdown voltage and lower Rds (i.e., drain-to-source resistance) in view of a typical MOSFET.
  • a super junction structure of the MOSFET is a region of alternating conductivity types in a substrate, such as the super junction structure includes p-type columns and n-type columns alternatively arranged in the substrate.
  • the p-type columns of the super junction structure are individually under source electrodes of the MOSFET, which however is difficult to have good performance and to integrate the MOSFET in a planar device.
  • multi-epi and doping processes with masks are required for the p-type columns and n-type columns, which results in poor uniformity, long process time and high cost.
  • FIGS. 1-7 are cross-sectional views of semiconductor devices having a super junction structure, in accordance with some embodiments.
  • FIGS. 8A-8E are cross-sectional views at various stages of fabricating a semiconductor device having a super junction structure, in accordance with some embodiments.
  • FIG. 9 is a flow chart illustrating a method for manufacturing a semiconductor device having a super junction structure, in accordance with some embodiments.
  • FIG. 10 is a cross-sectional view of a semiconductor device having a super junction structure, in accordance with some embodiments.
  • FIGS. 11A-11G are cross-sectional views at various stages of fabricating a super junction structure, in accordance with some embodiments.
  • FIG. 12 is a flow chart illustrating a method for manufacturing a super junction structure, in accordance with some embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • the p-type columns of the super junction structure are individually under source electrodes of the MOSFET, which however is difficult to have good performance and integrate the MOSFET in a planar device. Further, the p-type columns and n-type columns are fabricated by multi-epi and doping processes with masks, which however results in poor uniformity, long process time and high cost. To address the above issue, a semiconductor device having a super junction structure, a method for manufacturing the semiconductor device and a method for manufacturing the super junction structure are provided.
  • the semiconductor device of the present disclosure includes a pillar under a gate trench, which has better performance and makes it possible to integrate semiconductor device in a planar device.
  • the method for manufacturing the super junction structure includes forming a trench and a pillar of a conductivity type from an undoped material in the trench, which exhibits better uniformity, less process time and lower cost compared with fabrication of a super junction structure by the multi-epi process.
  • Embodiments of the semiconductor device having the super junction structure, the method for manufacturing the semiconductor device and the method for manufacturing the super junction structure are sequentially described below in detail.
  • FIG. 1 is a cross-sectional view of a semiconductor device 100 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 100 having a super junction structure includes a substrate 110 , an epitaxial layer 120 , a plurality of pillars 130 , a plurality of gate trenches 140 , an insulating layer 150 and a plurality of doped wells 160 .
  • the substrate 110 is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate 110 is an n-doped substrate. In some embodiments of the present disclosure, the n-type dopant includes, but not limited to, arsenic, phosphorous, another suitable n-type dopant or a combination thereof. In some embodiments of the present disclosure, the substrate 110 is a heavily doped substrate. In some embodiments of the present disclosure, the substrate 110 is acted as a drain electrode.
  • the substrate 110 includes, but not limited to, an elementary semiconductor including silicon or germanium in crystal, polycrystalline or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or a combination thereof; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; any other suitable material or combinations thereof.
  • an elementary semiconductor including silicon or germanium in crystal, polycrystalline or an amorphous structure
  • a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or a combination thereof
  • an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; any other
  • the epitaxial layer 120 of a first conductivity type is on the substrate 110 .
  • the epitaxial layer 120 is an n-doped epitaxial (n-epi) layer.
  • the epitaxial layer 120 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the pillars 130 of a second conductivity type are in the epitaxial layer 120 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 130 are p-doped pillars.
  • the pillars 130 include p-type dopants and thus can be acted as a p-type column.
  • the p-type dopants in the pillars 130 include boron, boron difluoride, another suitable p-type dopant or a combination thereof.
  • each of the pillars 130 is a multilayer structure. In some embodiments of the present disclosure, the multilayer structure is a multilayer of the second conductivity type. In some embodiments of the present disclosure, each of the pillars 130 is a p-doped multilayer structure. In some embodiments of the present disclosure, the multilayer structure of the pillars 130 is fabricated by multi-epi and doping processes with masks.
  • the gate trenches 140 are individually correspond to and over the pillars 130 , and the insulating layer 150 is in the gate trenches 140 .
  • the pillars 130 are individually in contact with the insulating layer 150 in the gate trenches 140 .
  • the insulating layer 150 includes a conductive material such as polysilicon or another suitable conductive material.
  • the insulating layer 150 includes a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the insulating layer 150 is an air gap.
  • the insulating layer 150 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 100 further includes another insulating layer between the insulating layer 150 and an inner surface of the gate trenches 140 .
  • the additional insulating layer includes silicon dioxide, aerogel, silicon nitride, silicon oxynitride, another suitable insulating material or a combination thereof.
  • the doped wells 160 of the second conductivity type are in the epitaxial layer 120 .
  • each of the doped wells 160 is between two adjacent gate trenches 140 .
  • the doped wells 160 are p-doped wells.
  • the doped wells 160 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 160 is in contact with a source electrode.
  • the p-type dopants in the doped wells 160 include boron, boron difluoride, another suitable p-type dopant or a combination thereof.
  • FIG. 2 is a cross-sectional view of a semiconductor device 200 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 200 having a super junction structure includes a substrate 210 , an epitaxial layer 220 , a plurality of pillars 230 , a plurality of gate trenches 240 , an insulating layer 250 and a plurality of doped wells 260 .
  • the substrate 210 is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate 210 is acted as a drain electrode.
  • the epitaxial layer 220 of a first conductivity type is on the substrate 210 . In some embodiments of the present disclosure, the epitaxial layer 220 is an n-epi layer.
  • the pillars 230 of a second conductivity type are in the epitaxial layer 220 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 230 are p-doped pillars.
  • the pillars 230 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 230 is a multilayer structure.
  • the multilayer structure is a multilayer of the second conductivity type.
  • each of the pillars 230 is a p-doped multilayer structure.
  • the gate trenches 240 are individually correspond to and over the pillars 230 , and the insulating layer 250 is in the gate trenches 240 .
  • the pillars 230 are individually in contact with the insulating layer 250 in the gate trenches 240 .
  • the insulating layer 250 includes an oxide layer 254 disposed on an inner surface of the gate trenches 240 ; and a polymer material 252 disposed on the oxide layer 254 and in the gate trenches 240 .
  • the polymer material 252 includes a conductive material such as polysilicon or another suitable conductive material.
  • the polymer material 252 and the oxide layer 254 individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the polymer material 252 includes an air gap.
  • the insulating layer 250 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 200 further includes another insulating layer between the insulating layer 250 and an inner surface of the gate trenches 240 .
  • the additional insulating layer includes silicon dioxide, aerogel, silicon nitride, silicon oxynitride, another suitable insulating material or a combination thereof.
  • the doped wells 260 of the second conductivity type are in the epitaxial layer 220 .
  • each of the doped wells 260 is between two adjacent gate trenches 240 .
  • the doped wells 260 are p-doped wells.
  • the doped wells 260 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 260 is in contact with a source electrode.
  • FIG. 3 is a cross-sectional view of a semiconductor device 300 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 300 having a super junction structure includes a substrate 310 , an epitaxial layer 320 , a plurality of pillars 330 , a plurality of gate trenches 340 , an insulating layer 350 , a plurality of doped wells 360 and a bury layer 370 .
  • the substrate 310 is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate 310 is a p-doped substrate. In some embodiments of the present disclosure, the substrate 310 includes p-type dopants and thus can be acted as a p-type base. In some embodiments of the present disclosure, the p-type dopants in the substrate 310 include boron, boron difluoride, another suitable p-type dopant or a combination thereof.
  • the epitaxial layer 320 of a first conductivity type is on the substrate 310 . In some embodiments of the present disclosure, the epitaxial layer 320 is an n-epi layer.
  • the bury layer 370 of the first conductivity type is between the substrate 310 and epitaxial layer 320 .
  • the bury layer 370 is an n-doped bury layer.
  • the bury layer 370 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the bury layer 370 is acted as an interlayer to conduct from a top source electrode to a top drain.
  • the pillars 330 of a second conductivity type are in the epitaxial layer 320 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 330 are p-doped pillars.
  • the pillars 330 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 330 is a multilayer structure.
  • the multilayer structure is a multilayer of the second conductivity type.
  • each of the pillars 330 is a p-doped multilayer structure.
  • the gate trenches 340 are individually correspond to and over the pillars 330 , and the insulating layer 350 is in the gate trenches 340 .
  • the pillars 330 are individually in contact with the insulating layer 350 in the gate trenches 340 .
  • the insulating layer 350 includes an oxide layer 354 disposed on an inner surface of the gate trenches 340 ; and a polymer material 352 disposed on the oxide layer 354 and in the gate trenches 340 .
  • the insulating layer 350 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 300 further includes another insulating layer between the insulating layer 350 and an inner surface of the gate trenches 340 .
  • the doped wells 360 of the second conductivity type are in the epitaxial layer 320 .
  • each of the doped wells 360 is between two adjacent gate trenches 340 .
  • the doped wells 360 are p-doped wells.
  • the doped wells 360 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 360 is in contact with a source electrode.
  • FIG. 4 is a cross-sectional view of a semiconductor device 400 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 400 having a super junction structure includes a substrate 410 , an epitaxial layer 420 , a plurality of pillars 430 , a plurality of gate trenches 440 , an insulating layer 450 and a plurality of doped wells 460 .
  • the substrate 410 is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate 410 is acted as a drain electrode.
  • the epitaxial layer 420 of a first conductivity type is on the substrate 410 . In some embodiments of the present disclosure, the epitaxial layer 420 is an n-epi layer.
  • the pillars 430 of a second conductivity type are in the epitaxial layer 420 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 430 are p-doped pillars.
  • the pillars 430 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 430 is a trench filled with the second conductivity type material.
  • the trench has a same pattern as that of the gate trenches.
  • the gate trenches 440 are individually correspond to and over the pillars 430 , and the insulating layer 450 is in the gate trenches 440 .
  • the pillars 430 are individually in contact with the insulating layer 450 in the gate trenches 440 .
  • the insulating layer 450 includes an oxide layer 454 disposed on an inner surface of the gate trenches 440 ; and a polymer material 452 disposed on the oxide layer 454 and in the gate trenches 440 .
  • the polymer material 452 includes a conductive material such as polysilicon or another suitable conductive material.
  • the polymer material 452 and the oxide layer 454 individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the polymer material 452 includes an air gap.
  • the insulating layer 450 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 400 further includes another insulating layer between the insulating layer 450 and an inner surface of the gate trenches 440 .
  • the doped wells 460 of the second conductivity type are in the epitaxial layer 420 .
  • each of the doped wells 460 is between two adjacent gate trenches 440 .
  • the doped wells 460 are p-doped wells.
  • the doped wells 460 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 460 is in contact with a source electrode.
  • FIG. 5 is a cross-sectional view of a semiconductor device 500 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 500 having a super junction structure includes a substrate 510 , an epitaxial layer 520 , a plurality of pillars 530 , a plurality of gate trenches 540 , an insulating layer 550 , a plurality of doped wells 560 and a bury layer 570 .
  • the substrate 510 is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate 510 is a p-doped substrate. In some embodiments of the present disclosure, the substrate 510 includes p-type dopants and thus can be acted as a p-type base.
  • the epitaxial layer 520 of a first conductivity type is on the substrate 510 . In some embodiments of the present disclosure, the epitaxial layer 520 is an n-epi layer.
  • the bury layer 570 of the first conductivity type is between the substrate 510 and epitaxial layer 520 .
  • the bury layer 570 is an n-doped bury layer.
  • the bury layer 570 is acted as an interlayer to conduct from a top source electrode to a top drain.
  • the pillars 530 of a second conductivity type are in the epitaxial layer 520 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 530 are p-doped pillars.
  • the pillars 530 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 530 is a trench filled with the second conductivity type material. In some embodiments of the present disclosure, the trench has a same pattern as that of the gate trenches.
  • the gate trenches 540 are individually correspond to and over the pillars 530 , and the insulating layer 550 is in the gate trenches 540 .
  • the pillars 530 are individually in contact with the insulating layer 550 in the gate trenches 540 .
  • the insulating layer 550 includes an oxide layer 554 disposed on an inner surface of the gate trenches 540 ; and a polymer material 552 disposed on the oxide layer 554 and in the gate trenches 540 .
  • the polymer material 552 includes an air gap.
  • the insulating layer 550 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 500 further includes another insulating layer between the insulating layer 550 and an inner surface of the gate trenches 540 .
  • the doped wells 560 of the second conductivity type are in the epitaxial layer 520 .
  • each of the doped wells 560 is between two adjacent gate trenches 540 .
  • the doped wells 560 are p-doped wells.
  • the doped wells 560 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 560 is in contact with a source electrode.
  • FIG. 6 is a cross-sectional view of a semiconductor device 600 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 600 having a super junction structure includes a substrate 610 , an epitaxial layer 620 , a plurality of pillars 630 , a plurality of gate trenches 640 , an insulating layer 650 and a plurality of doped wells 660 .
  • the substrate 610 is a doped substrate of the first conductivity type. In some embodiments of the present disclosure, the substrate 610 is acted as a drain electrode.
  • the epitaxial layer 620 of a first conductivity type is on the substrate 610 . In some embodiments of the present disclosure, the epitaxial layer 620 is an n-epi layer.
  • the pillars 630 of a second conductivity type are in the epitaxial layer 620 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 630 are p-doped pillars.
  • the pillars 630 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 630 is a trench filled with the second conductivity type material.
  • the trench is an angled trench.
  • the trench has a same pattern as that of the gate trenches.
  • the gate trenches 640 are individually correspond to and over the pillars 630 , and the insulating layer 650 is in the gate trenches 640 .
  • the pillars 630 are individually in contact with the insulating layer 650 in the gate trenches 640 .
  • the insulating layer 650 includes an oxide layer 654 disposed on an inner surface of the gate trenches 640 ; and a polymer material 652 disposed on the oxide layer 654 and in the gate trenches 640 .
  • the polymer material 652 includes a conductive material such as polysilicon or another suitable conductive material.
  • the polymer material 652 and the oxide layer 654 individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the polymer material 652 includes an air gap.
  • the insulating layer 650 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 600 further includes another insulating layer between the insulating layer 650 and an inner surface of the gate trenches 640 .
  • the doped wells 660 of the second conductivity type are in the epitaxial layer 620 .
  • each of the doped wells 660 is between two adjacent gate trenches 640 .
  • the doped wells 660 are p-doped wells.
  • the doped wells 660 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 660 is in contact with a source electrode.
  • FIG. 7 is a cross-sectional view of a semiconductor device 700 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 700 having a super junction structure includes a substrate 710 , an epitaxial layer 720 , a plurality of pillars 730 , a plurality of gate trenches 740 , an insulating layer 750 , a plurality of doped wells 760 and a bury layer 770 .
  • the substrate 710 is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate 710 is a p-doped substrate. In some embodiments of the present disclosure, the substrate 710 includes p-type dopants and thus can be acted as a p-type base.
  • the epitaxial layer 720 of a first conductivity type is on the substrate 710 . In some embodiments of the present disclosure, the epitaxial layer 720 is an n-epi layer.
  • the bury layer 770 of the first conductivity type is between the substrate 710 and epitaxial layer 720 .
  • the bury layer 770 is an n-doped bury layer.
  • the bury layer 770 is acted as an interlayer to conduct from a top source electrode to a top drain.
  • the pillars 730 of a second conductivity type are in the epitaxial layer 720 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 730 are p-doped pillars.
  • the pillars 630 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 730 is a trench filled with the second conductivity type material.
  • the trench is an angled trench.
  • the trench has a same pattern as that of the gate trenches.
  • the gate trenches 740 are individually correspond to and over the pillars 730 , and the insulating layer 750 is in the gate trenches 740 .
  • the pillars 730 are individually in contact with the insulating layer 750 in the gate trenches 740 .
  • the insulating layer 750 includes an oxide layer 754 disposed on an inner surface of the gate trenches 740 ; and a polymer material 752 disposed on the oxide layer 754 and in the gate trenches 740 .
  • the polymer material 752 includes a conductive material such as polysilicon or another suitable conductive material.
  • the polymer material 752 and the oxide layer 754 individually include a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the polymer material 752 includes an air gap.
  • the insulating layer 750 can be acted as a gate insulating layer and in contact with a gate electrode.
  • the semiconductor device 700 further includes another insulating layer between the insulating layer 750 and an inner surface of the gate trenches 740 .
  • the doped wells 660 of the second conductivity type are in the epitaxial layer 720 .
  • each of the doped wells 760 is between two adjacent gate trenches 740 .
  • the doped wells 760 are p-doped wells.
  • the doped wells 760 include p-type dopants and thus can be acted as a p-type semiconductor wells.
  • each of the doped wells 760 is in contact with a source electrode.
  • FIGS. 8A-8E are cross-sectional views at various stages of fabricating a semiconductor device 800 having a super junction structure, in accordance with some embodiments.
  • a substrate 810 is provided, and an epitaxial layer 820 of a first conductivity type is then formed on the substrate 810 .
  • the epitaxial layer 820 is formed on the substrate 810 by an epitaxial process.
  • the epitaxial layer 820 is a first conductivity type.
  • the epitaxial layer 820 is formed an n-type epitaxial layer.
  • the epitaxial layer 820 is doped by introducing dopants during the formation of the epitaxial layer 820 .
  • the epitaxial layer 820 is doped after formation of the epitaxial layer 820 .
  • a bury layer of the first conductivity type is formed between the substrate 810 and the epitaxial layer 820 .
  • the bury layer is formed an n-doped bury layer.
  • the bury layer is formed of silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the bury layer is formed to be acted as an interlayer to conduct from a top source electrode to a top drain.
  • the bury layer is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, another suitable formation process or a combination thereof.
  • ion implantation is performed to deposit dopants of a second conductivity type into the epitaxial layer 820 , so as to form a doped layer 830 of the second conductivity type in the epitaxial layer 820 .
  • a vertical ion implantation process is performed on the epitaxial layer 820 .
  • a tilt ion implantation process is performed on the epitaxial layer 820 .
  • the doped layer 830 is a second conductivity type opposite to the first conductivity type.
  • the ion implantation deposits p-type dopants into the epitaxial layer 820 .
  • the p-type dopants include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.
  • a plurality of gate trenches 840 are formed in the doped layer 830 and the epitaxial layer 820 .
  • a hard mask layer is formed over the doped layer 830 .
  • a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer.
  • the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material.
  • the hard mask layer exposes a portion of the doped layer 830 for forming the gate trenches 840 .
  • the exposed portion of the doped layer 830 is removed according to the hard mask layer to form the gate trenches 840 in the doped layer 830 and the epitaxial layer 820 .
  • a part of the doped layer 830 and a part of the epitaxial layer 820 are removed by a dry etching process.
  • the etchant includes carbon fluorides (C x F y ), sulfur hexafluoride (SF 6 ), oxygen gas (O 2 ), helium (He), carbon chlorides (C x Cl y ), argon (Ar), another suitable etchant material or a combination thereof.
  • the gate trenches 840 are a straight walled trench or an angled trench. In the embodiment of FIG. 8C , the gate trenches 840 are straight walled trenches.
  • ion implantation is performed to deposit dopants 852 of a second conductivity type into the gate trenches 840 , so as to form a plurality of pillars 850 in the epitaxial layer 820 and individually correspond to and under the gate trenches 840 .
  • a vertical ion implantation process is performed into the gate trenches 840 .
  • the pillars 850 are a second conductivity type.
  • the ion implantation deposits p-type dopants into the gate trenches 840 , so as to form a p-doped pillar 850 .
  • the p-type dopants include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.
  • the formation of the pillars 850 includes forming a trench filled with the second conductivity type material or forming a multilayer structure. In some embodiments of the present disclosure, the formation of the trench includes forming an angled trench, and then a second conductivity type material is filled in the trench by an epitaxial method. In some embodiments of the present disclosure, a pattern of the trench is formed the same as that of the gate trenches 840 .
  • each of the pillars 850 is formed a multilayer structure.
  • the formation of the multilayer structure includes forming a multilayer of the second conductivity type by performing an ion implantation.
  • each of the pillars 850 is formed a p-doped multilayer structure.
  • the multilayer structure of the pillars 850 is fabricated by multi-epi and doping processes with masks.
  • the hard mask layer is removed.
  • the hard mask layer is removed by an etching process, a planarization process, another suitable material removal process or a combination thereof.
  • an insulating layer 860 is filled in the gate trenches 840 .
  • the insulating layer 860 is omitted.
  • the insulating layer 860 is formed after formation of another insulating layer.
  • the insulating layer 860 includes silicon dioxide, aerogel, another suitable insulating material or a combination thereof.
  • the insulating layer 860 is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.
  • the insulating layer 860 includes a conductive material such as polysilicon or another suitable conductive material.
  • the insulating layer 860 includes a dielectric material, such as silicon dioxide, a silicon nitride or another suitable dielectric material.
  • the insulating layer 860 includes an air gap.
  • the formation of the insulating layer further includes forming an oxide layer on an inner surface of the gate trenches; and filling a polymer material in the gate trenches.
  • a planarization process is performed.
  • the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof.
  • CMP chemical mechanical polishing
  • the planarization process removes portions of the insulating layer 860 outside the gate trenches 840 .
  • a top surface of the insulating layer 860 and a top surface of the doped wells are coplanar.
  • FIG. 9 is a flow chart illustrating a method for manufacturing a semiconductor device having a super junction structure, in accordance with some embodiments.
  • the operations 901 to 905 are disclosed in association with the cross-sectional views of the integrated circuit structure 800 from FIGS. 8A to 8E at various fabrication stages.
  • the substrate 810 is provided, and the epitaxial layer 820 of a first conductivity type is then formed on the substrate 810 .
  • the epitaxial layer 820 is formed on the substrate 810 by an epitaxial process.
  • the epitaxial layer 820 is a first conductivity type.
  • the epitaxial layer 820 is formed an n-type epitaxial layer.
  • a bury layer of the first conductivity type is formed between the substrate 810 and the epitaxial layer 820 .
  • the bury layer is formed an n-doped bury layer.
  • ion implantation is performed to deposit dopants of the second conductivity type into the epitaxial layer 820 , so as to form the doped layer 830 of the second conductivity type in the epitaxial layer 820 .
  • the doped layer 830 is a second conductivity type opposite to the first conductivity type.
  • the ion implantation deposits p-type dopants into the epitaxial layer 820 .
  • the gate trenches 840 are formed in the doped layer 830 and the epitaxial layer 820 .
  • a hard mask layer is formed over the doped layer 830 .
  • the hard mask layer exposes a portion of the doped layer 830 for forming the gate trenches 840 .
  • the exposed portion of the doped layer 830 is removed according to the hard mask layer to form the gate trenches 840 in the doped layer 830 and the epitaxial layer 820 .
  • a part of the doped layer 830 and a part of the epitaxial layer 820 are removed by a dry etching process.
  • the gate trenches 840 are straight walled trenches.
  • ion implantation is performed to deposit dopants 852 of the second conductivity type into the gate trenches 840 , so as to form the pillars 850 in the epitaxial layer 820 and individually correspond to and under the gate trenches 840 .
  • a vertical ion implantation process is performed into the gate trenches 840 .
  • the pillars 850 are a second conductivity type.
  • the ion implantation deposits p-type dopants into the gate trenches 840 , so as to form a p-doped pillar 850 .
  • the formation of the pillars 850 includes forming a trench filled with the second conductivity type material or forming a multilayer structure. In some embodiments of the present disclosure, the formation of the trench includes forming an angled trench, and then a second conductivity type material is filled in the trench by an epitaxial method. In some embodiments of the present disclosure, a pattern of the trench is formed the same as that of the gate trenches 840 .
  • each of the pillars 850 is formed a multilayer structure.
  • the formation of the multilayer structure includes forming a multilayer of the second conductivity type by performing an ion implantation.
  • each of the pillars 850 is formed a p-doped multilayer structure.
  • the multilayer structure of the pillars 850 is fabricated by multi-epi and doping processes with masks. In some embodiments of the present disclosure, after the dopants 852 are deposited, the hard mask layer is removed.
  • an insulating layer 860 is filled in the gate trenches 840 .
  • the insulating layer 860 is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.
  • the formation of the insulating layer further includes forming an oxide layer on an inner surface of the gate trenches; and filling a polymer material in the gate trenches.
  • a planarization process is performed.
  • the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof.
  • CMP chemical mechanical polishing
  • the planarization process removes portions of the insulating layer 860 outside the gate trenches 840 .
  • a top surface of the insulating layer 860 and a top surface of the doped wells are coplanar.
  • FIG. 10 is a cross-sectional view of a semiconductor device 1000 having a super junction structure, in accordance with some embodiments.
  • the semiconductor device 1000 having a super junction structure includes a substrate 1010 , an epitaxial layer 1020 , a plurality of pillars 1030 , a plurality of gate trenches 1040 , an insulating layer 1050 , a plurality of doped wells 1060 , a bury layer 1070 and a doped column 1080 .
  • the semiconductor device 1000 having a super junction structure further includes a cell region 1001 and a terminal region 1002 adjacent to the cell region 1001 .
  • the pillars 1030 , the gate trenches 1040 , the insulating layer 1050 and the doped wells 1060 are positioned in the cell region 1001 ; and the doped column 1080 is positioned in the terminal region 1002 .
  • the substrate 1010 is a doped substrate of the second conductivity type. In some embodiments of the present disclosure, the substrate 1010 is a p-doped substrate. In some embodiments of the present disclosure, the substrate 1010 includes p-type dopants and thus can be acted as a p-type base. In some embodiments of the present disclosure, the p-type dopants in the substrate 1010 include boron, boron difluoride, another suitable p-type dopant or a combination thereof.
  • the epitaxial layer 1020 of a first conductivity type is on the substrate 1010 . In some embodiments of the present disclosure, the epitaxial layer 1020 is an n-epi layer.
  • the bury layer 1070 of the first conductivity type is between the substrate 1010 and epitaxial layer 1020 .
  • the bury layer 1070 is an n-doped bury layer.
  • the bury layer 1070 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the pillars 1030 of a second conductivity type are in the epitaxial layer 1020 .
  • the second conductivity type is opposite to the first conductivity type.
  • the pillars 1030 are p-doped pillars.
  • the pillars 1030 include p-type dopants and thus can be acted as a p-type column.
  • each of the pillars 1030 is a multilayer structure.
  • the multilayer structure is a multilayer of the second conductivity type.
  • each of the pillars 1030 is a p-doped multilayer structure.
  • the gate trenches 1040 are individually correspond to and over the pillars 1030 , and the insulating layer 1050 is in the gate trenches 340 .
  • the pillars 1030 are individually in contact with the insulating layer 1050 in the gate trenches 1040 .
  • the insulating layer 1050 includes an oxide layer 1054 disposed on an inner surface of the gate trenches 1040 ; and a polymer material 1052 disposed on the oxide layer 1054 and in the gate trenches 1040 .
  • the insulating layer 1050 can be acted as a gate insulating layer and in contact with a gate electrode 1051 .
  • the semiconductor device 1000 further includes another insulating layer between the insulating layer 1050 and an inner surface of the gate trenches 1040 .
  • the doped wells 1060 are in the epitaxial layer 1020 . In some embodiments of the present disclosure, each of the doped wells 1060 is between two adjacent gate trenches 1040 . In some embodiments of FIG. 10 , each of the doped wells 1060 includes a p-doped well 1062 , a heavily p-doped well 1068 and two heavily n-doped wells 1064 and 1066 . In some embodiments of the present disclosure, the heavily n-doped wells 1064 and 1066 are disposed on the p-doped well 1062 , and are not in contact with each other.
  • the heavily p-doped well 1068 is disposed on the p-doped well 1062 and sandwiched between the heavily n-doped wells 1064 and 1066 .
  • a source electrode 1061 is sandwiched between the heavily n-doped wells 1064 and 1066 and in contact with the heavily p-doped well 1068 .
  • the doped column 1080 is in the epitaxial layer 1020 and in contact with the bury layer 1070 .
  • the doped column 1080 is the first conductivity type.
  • the doped column 1080 is an n-doped bury layer.
  • the doped column 1080 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the bury layer 1070 and the doped column 1080 are formed to act as an interlayer to conduct from the top source electrode 1061 to a top drain 1081 .
  • the top drain 1081 is in contact with a top surface of the doped column 1080 .
  • a heavily n-doped well 1082 is further sandwiched between the top drain 1081 and the doped column 1080 .
  • FIGS. 11A-11G are cross-sectional views at various stages of fabricating a super junction structure 1100 , in accordance with some embodiments.
  • a plurality of trenches 1120 are formed in a substrate 1110 a of a first conductivity type.
  • the substrate 1110 a is an n-doped substrate.
  • the n-type dopant includes, but not limited to, arsenic, phosphorous, another suitable n-type dopant or a combination thereof.
  • the substrate 1110 a is a heavily doped substrate.
  • the substrate 1110 a is acted as a drain electrode.
  • the substrate 1110 a includes, but not limited to, an elementary semiconductor including silicon or germanium in crystal, polycrystalline or an amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or a combination thereof; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; any other suitable material or combinations thereof.
  • a hard mask layer is formed over the substrate 1110 a.
  • a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer.
  • the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material.
  • the hard mask layer exposes a portion of the substrate 1110 a for forming the trenches 1120 .
  • the exposed portion of the substrate 1110 a is removed according to the hard mask layer to form the trenches 1120 in the substrate 1110 a.
  • a part of the substrate 1110 a is removed by a dry etching process.
  • the etchant includes carbon fluorides (C x F y ), sulfur hexafluoride (SF 6 ), oxygen gas (O 2 ), helium (He), carbon chlorides (C x Cl y ), argon (Ar), another suitable etchant material or a combination thereof.
  • the trenches 1120 are formed angled trenches.
  • the trenches 1120 are formed in an epitaxial layer 1112 of the first conductivity type, wherein the epitaxial layer 1112 is deposited on the substrate 1110 a.
  • the epitaxial layer 1112 is an n-doped epitaxial (n-epi) layer.
  • the epitaxial layer 1112 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • a hard mask layer is formed over the epitaxial layer 1112 .
  • a hard mask material is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, spin-on coating, or another suitable formation process, and then patterned by a photolithography/etching process, a laser drilling process or another suitable material removal process to form the hard mask layer.
  • the hard mask layer includes silicon dioxide, silicon nitride or another suitable masking material.
  • the hard mask layer exposes a portion of the epitaxial layer 1112 for forming the trenches 1120 .
  • the exposed portion of the epitaxial layer 1112 is removed according to the hard mask layer to form the trenches 1120 in the epitaxial layer 1112 .
  • a part of the substrate 1110 a is removed by a dry etching process.
  • the etchant includes carbon fluorides (C x F y ), sulfur hexafluoride (SF 6 ), oxygen gas (O 2 ), helium (He), carbon chlorides (C x Cl y ), argon (Ar), another suitable etchant material or a combination thereof.
  • the trenches 1120 are formed angled trenches.
  • the trenches 1120 are formed in an epitaxial layer 1112 of the first conductivity type, wherein the epitaxial layer 1112 is deposited on the substrate 1110 b.
  • the substrate 1110 b is a second conductivity type opposite to the first conductivity type.
  • the substrate 1110 b is a doped substrate of the second conductivity type.
  • the substrate 1110 b is a p-doped substrate.
  • the substrate 1110 b includes p-type dopants and thus can be acted as a p-type base.
  • the p-type dopants in the substrate 1110 b include boron, boron difluoride, another suitable p-type dopant or a combination thereof.
  • the epitaxial layer 1112 of a first conductivity type is on the substrate 1110 b. In some embodiments of the present disclosure, the epitaxial layer 1112 is an n-epi layer.
  • a bury layer 1114 of the first conductivity type is sandwiched between the epitaxial layer 1112 and the substrate 1110 b.
  • the bury layer 1114 is an n-doped bury layer.
  • the bury layer 1114 includes silicon, germanium, another suitable n-type semiconductor material or the combination thereof.
  • the bury layer 1114 is acted as an interlayer to conduct from a top source electrode to a top drain.
  • ion implantation is performed to deposit dopants 1132 of the second conductivity type into the trenches 1120 , so as to form a doped region 1130 of the second conductivity type in the substrate 1110 a and surrounding the trenches 1120 .
  • a tilt and vertical ion implantation process is performed into the trenches 1120 .
  • the ion implantation deposits p-type dopants 1132 into the trenches 1120 , so as to form a p-doped region 1130 in the substrate 1110 a and surrounding the trenches 1120 .
  • the p-type dopants 1132 include, but not limited to, boron, boron difluoride, another suitable p-type dopant, or a combination thereof.
  • an undoped material 1140 is filled in the trenches 1120 .
  • filling the undoped material 1140 in the trenches 1120 includes depositing an undoped polymer material in the trenches 1120 .
  • the undoped material 1140 includes a conductive material such as polysilicon, another suitable conductive material or a combination thereof.
  • the undoped material 1140 is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.
  • a planarization process is performed.
  • the planarization process removes portions of the undoped material 1140 outside the trenches 1120 .
  • a top surface of the undoped material 1140 and a top surface of the substrate 1110 a are coplanar.
  • the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another suitable material removal process or a combination thereof.
  • CMP chemical mechanical polishing
  • a pillar 1150 of the second conductivity type is formed from the undoped material 1140 in the trenches 1120 .
  • the formation of the pillar 1150 includes performing a thermal diffusion process to diffuse the doped region 1130 of the second conductivity type surrounding the trenches 1120 into the undoped material 1140 in the trenches 1120 , so as to form the pillar 1150 of the second conductivity type.
  • the thermal process diffuses the p-type dopants 1132 from the doped region 1130 into the undoped material 1140 in the trenches 1120 , so as to form the p-doped pillar 1150 in the substrate 1110 a.
  • the pillar 1150 of the second conductivity type is formed under a gate trench or a doped well of a second conductivity type.
  • FIG. 12 is a flow chart illustrating a method for manufacturing a super junction structure, in accordance with some embodiments.
  • the operations 1201 to 1204 are disclosed in association with the cross-sectional views of the integrated circuit structure 1100 from FIGS. 11A, 11D to 11G at various fabrication stages.
  • the trenches 1120 are formed in the substrate 1110 a of the first conductivity type.
  • the substrate 1110 a is an n-doped substrate.
  • a hard mask layer is formed over the substrate 1110 a.
  • the hard mask layer exposes a portion of the substrate 1110 a for forming the trenches 1120 .
  • the exposed portion of the substrate 1110 a is removed according to the hard mask layer to form the trenches 1120 in the substrate 1110 a.
  • a part of the substrate 1110 a is removed by a dry etching process. Referring to FIG. 11A , the trenches 1120 are formed angled trenches.
  • the doped region 1130 of the second conductivity type is formed in the substrate 1110 a and surrounding the trenches 1120 .
  • ion implantation is performed to deposit dopants 1132 of the second conductivity type into the trenches 1120 .
  • the doped region 1130 is formed in the substrate 1110 a and surrounding the trenches 1120 .
  • a tilt and vertical ion implantation process is performed into the trenches 1120 .
  • the ion implantation deposits p-type dopants 1132 into the trenches 1120 , so as to form a p-doped region 1130 in the substrate 1110 a and surrounding the trenches 1120 .
  • the undoped material 1140 is filled in the trenches 1120 .
  • filling the undoped material 1140 in the trenches 1120 includes depositing an undoped polymer material in the trenches 1120 .
  • the undoped material 1140 is blanket deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, a spin-on process or another suitable formation process.
  • a planarization process is performed. In some embodiments of the present disclosure, the planarization process removes portions of the undoped material 1140 outside the trenches 1120 . In some embodiments of the present disclosure, after the planarization process, a top surface of the undoped material 1140 and a top surface of the substrate 1110 a are coplanar.
  • the pillar 1150 of the second conductivity type is formed from the undoped material 1140 in the trenches 1120 .
  • the formation of the pillar 1150 includes performing a thermal diffusion process to diffuse the doped region 1130 of the second conductivity type surrounding the trenches 1120 into the undoped material 1140 in the trenches 1120 , so as to form the pillar 1150 of the second conductivity type.
  • the thermal process diffuses the p-type dopants 1132 from the doped region 1130 into the undoped material 1140 in the trenches 1120 , so as to form the p-doped pillar 1150 in the substrate 1110 a.
  • the pillar 1150 of the second conductivity type is formed under a gate trench or a doped well of a second conductivity type.
  • a semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type.
  • the epitaxial layer of the first conductivity type is on the substrate.
  • the pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type.
  • the gate trenches are individually corresponding to and over the pillars.
  • the insulating layer is in the gate trenches.
  • the doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches.
  • a method for manufacturing a semiconductor device having a super junction structure includes: forming an epitaxial layer on a substrate, in which the epitaxial layer is a first conductivity type; forming a doped layer in the epitaxial layer, in which the doped layer is a second conductivity type opposite to the first conductivity type; forming a plurality of gate trenches in the doped layer and the epitaxial layer; forming a plurality of pillars in the epitaxial layer and individually correspond to and under the gate trenches; and filling an insulating material in the gate trenches.
  • a method for manufacturing a super junction structure includes: forming a plurality of trenches in a substrate of a first conductivity type; forming a doped region of a second conductivity type in the substrate and surrounding the trenches, in which the second conductivity type is opposite to the first conductivity type; filling an undoped material in the trenches; and forming a pillar of the second conductivity type from the undoped material in the trenches.

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CN116682734B (zh) * 2023-07-28 2023-10-13 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法
CN116666222A (zh) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 一种Trench MOS器件及其制备方法

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CN105632931B (zh) 2020-04-28
US12040358B2 (en) 2024-07-16

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