JP2014187237A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014187237A JP2014187237A JP2013061474A JP2013061474A JP2014187237A JP 2014187237 A JP2014187237 A JP 2014187237A JP 2013061474 A JP2013061474 A JP 2013061474A JP 2013061474 A JP2013061474 A JP 2013061474A JP 2014187237 A JP2014187237 A JP 2014187237A
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Abstract
【解決手段】ドリフト層DRTには、埋込第2導電型層DIF1及び下側第2導電型層DIF3が形成されている。埋込第2導電型層DIF1の側部とドリフト層DRTの境界には、境界絶縁膜SINS1が形成されている。下側第2導電型層DIF3は、埋込第2導電型層DIF1の下端及び境界絶縁膜SINS1の下端に接している。そして埋込第2導電型層DIF1は、ソース電極SOEに電気的に接続している。埋込第2導電型層DIF1の表層には高濃度第2導電型層DIF2が形成されている。
【選択図】図1
Description
その他の課題と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。
図1は、第1の実施形態に係る半導体装置SDの上面図である。図2は、図1からゲートパッドGEP1、ゲート配線GEI2、及びソース電極SOEを取り除いた図である。
図11は、第2の実施形態に係る半導体装置SDにおける、高濃度第2導電型層DIF2とコンタクトDICの接続部の構造を示す断面図であり、第1の実施形態における図3に対応している。本実施形態に係る半導体装置SDは、この接続部の構造を除いて、第1の実施形態に係る半導体装置SDと同様の構成である。
図12は、第3の実施形態に係る半導体装置SDの構成を示す断面図であり、第1の実施形態における図4に対応している。本実施形態に係る半導体装置SDは、埋込第2導電型層DIF1が多層構造になっている点を除いて、第1又は第2の実施形態と同様の構成である。埋込第2導電型層DIF1の多層構造は、成膜工程及びエッチバック工程を複数回繰り返すことにより、得られる。本図に示す例において、埋込第2導電型層DIF1は、埋込第2導電型層DIF11,DIF12をこの順に積層した2層構造になっている。
図13は、第4の実施形態に係る半導体装置SDの構成を示す断面図であり、第1の実施形態における図4に対応している。本実施形態に係る半導体装置SDは、以下の点を除いて、第1〜第3の実施形態のいずれかに係る半導体装置SDと同様の構成である。
図14は、第5の実施形態に係る半導体装置SDの構成を示す図である。本図に示す例は、以下の点を除いて、第4の実施形態に係る半導体装置SDと同様の構成である。
BSE ベース層
BSUB ベース基板
DEPI 埋込絶縁膜
DGE ダミーゲート電極
DIC コンタクト
DIF1 埋込第2導電型層
DIF11 埋込第2導電型層
DIF12 埋込第2導電型層
DIF2 高濃度第2導電型層
DIF2E 露出領域
DIF3 下側第2導電型層
DINS 熱酸化膜
DRE ドレイン電極
DRN ドレイン層
DRT ドリフト層
EPI エピタキシャル層
GE ゲート電極
GEC1 コンタクト
GEC2 コンタクト
GEI1 ゲート配線
GEI2 ゲート配線
GEP1 ゲートパッド
GEP2 下層パッド
GINS ゲート絶縁膜
GTRN ゲートトレンチ
INSL 層間絶縁膜
MSK1 マスク膜
OP1 開口
OP2 開口
RST レジストパターン
SBC コンタクト
SBC コンタクト
SD 半導体装置
SOC コンタクト
SOE ソース電極
SOU ソース層
SUB 半導体基板
VINC 埋込導電層
Claims (7)
- 第1の第1導電型層と、
前記第1の第1導電型層上に形成された第2導電型層と、
前記第2導電型層上に形成された第2の第1導電型層と、
前記第2の第1導電型層及び前記第2導電型層を貫通しており、下端が前記第1の第1導電型層に達しているゲートトレンチと、
前記ゲートトレンチの内壁に形成されたゲート絶縁膜と、
前記ゲートトレンチ内に埋め込まれたゲート電極と、
前記第1の第1導電型層に形成された埋込第2導電型層と、
前記埋込第2導電型層の側部と前記第1の第1導電型層の境界に位置する境界絶縁膜と、
前記第1の第1導電型層に形成され、前記埋込第2導電型層及び前記境界絶縁膜の下端に接している下側第2導電型層と、
前記第2の第1導電型層より上に形成され、前記埋込第2導電型層に電気的に接続する電極と、
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記下側第2導電型層は、平面視で前記埋込第2導電型層の全てを覆っている半導体装置。 - 請求項1に記載の半導体装置において、
少なくとも一部が前記埋込第2導電型層の表層に位置し、前記埋込第2導電型層よりも不純物濃度が高い高濃度第2導電型層を備え、
前記電極は、前記高濃度第2導電型層に接続している半導体装置。 - 請求項1に記載の半導体装置において、
前記埋込第2導電型層は平面視で前記ゲート電極と重なっており、
前記境界絶縁膜の上部は、前記ゲート絶縁膜の下部と接続している半導体装置。 - 請求項1に記載の半導体装置において、
平面視において、前記埋込第2導電型層及び前記境界絶縁膜は、前記ゲート電極及び前記ゲート絶縁膜と並んでいる半導体装置。 - 請求項5に記載の半導体装置において、
前記ゲートトレンチは複数互いに並んで形成されており、
前記複数のゲートトレンチのそれぞれには、前記ゲート絶縁膜及び前記ゲート電極が形成されており、
前記埋込第2導電型層及び前記境界絶縁膜は、平面視で前記複数のゲートトレンチの間に位置する半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の第1導電型層に接続されたドレイン電極と、
前記第2の第1導電型層に接続されたソース電極と、
を備え、
前記ドレイン電極と前記ソース電極の間に60V以上の電圧が印加される半導体装置。
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