JP6936454B2 - 高電圧隔離のためのデュアルディープトレンチ - Google Patents

高電圧隔離のためのデュアルディープトレンチ Download PDF

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JP6936454B2
JP6936454B2 JP2019509513A JP2019509513A JP6936454B2 JP 6936454 B2 JP6936454 B2 JP 6936454B2 JP 2019509513 A JP2019509513 A JP 2019509513A JP 2019509513 A JP2019509513 A JP 2019509513A JP 6936454 B2 JP6936454 B2 JP 6936454B2
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trench
substrate
layer
integrated circuit
conductor
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JP2019526932A (ja
JP2019526932A5 (enExample
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ペンハルカル サミール
ペンハルカル サミール
フー ビンホワ
フー ビンホワ
サドブニコフ アレクセイ
サドブニコフ アレクセイ
マトゥール グル
マトゥール グル
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テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
JP2019509513A 2016-08-16 2017-08-16 高電圧隔離のためのデュアルディープトレンチ Active JP6936454B2 (ja)

Priority Applications (1)

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JP2021133052A JP7293293B2 (ja) 2016-08-16 2021-08-18 高電圧隔離のためのデュアルディープトレンチ

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/238,198 2016-08-16
US15/238,198 US9786665B1 (en) 2016-08-16 2016-08-16 Dual deep trenches for high voltage isolation
PCT/US2017/047151 WO2018035229A2 (en) 2016-08-16 2017-08-16 Dual deep trenches for high voltage isolation

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JP2019526932A JP2019526932A (ja) 2019-09-19
JP2019526932A5 JP2019526932A5 (enExample) 2020-09-24
JP6936454B2 true JP6936454B2 (ja) 2021-09-15

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JP2021133052A Active JP7293293B2 (ja) 2016-08-16 2021-08-18 高電圧隔離のためのデュアルディープトレンチ

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US (2) US9786665B1 (enExample)
EP (1) EP3501040B1 (enExample)
JP (2) JP6936454B2 (enExample)
CN (1) CN109564895B (enExample)
WO (1) WO2018035229A2 (enExample)

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US9786665B1 (en) * 2016-08-16 2017-10-10 Texas Instruments Incorporated Dual deep trenches for high voltage isolation
US10262997B2 (en) * 2017-09-14 2019-04-16 Vanguard International Semiconductor Corporation High-voltage LDMOSFET devices having polysilicon trench-type guard rings
CN111341847B (zh) * 2018-12-19 2023-03-28 联华电子股份有限公司 半导体结构及其制作方法
US10811543B2 (en) * 2018-12-26 2020-10-20 Texas Instruments Incorporated Semiconductor device with deep trench isolation and trench capacitor
US11158750B2 (en) 2019-07-03 2021-10-26 Texas Instruments Incorporated Superlattice photo detector
US11502036B2 (en) * 2020-02-07 2022-11-15 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
DE112021006557B4 (de) 2021-01-15 2025-02-20 Rohm Co., Ltd. Halbleitervorrichtungen
JP7724087B2 (ja) * 2021-06-16 2025-08-15 ローム株式会社 半導体装置および半導体装置の製造方法
JP7748832B2 (ja) * 2021-08-26 2025-10-03 ローム株式会社 半導体装置
US12087813B2 (en) * 2021-08-31 2024-09-10 Texas Instruments Incorporated Deep trench isolation with field oxide
US12159910B2 (en) * 2022-02-15 2024-12-03 Globalfoundries U.S. Inc. Isolation regions for charge collection and removal

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US6316336B1 (en) * 1999-03-01 2001-11-13 Richard A. Blanchard Method for forming buried layers with top-side contacts and the resulting structure
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US9786665B1 (en) * 2016-08-16 2017-10-10 Texas Instruments Incorporated Dual deep trenches for high voltage isolation

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Publication number Publication date
EP3501040A4 (en) 2019-06-26
WO2018035229A2 (en) 2018-02-22
JP7293293B2 (ja) 2023-06-19
JP2019526932A (ja) 2019-09-19
US20180053765A1 (en) 2018-02-22
CN109564895A (zh) 2019-04-02
WO2018035229A3 (en) 2018-04-05
CN109564895B (zh) 2023-08-11
EP3501040A2 (en) 2019-06-26
JP2021184491A (ja) 2021-12-02
EP3501040B1 (en) 2022-04-27
US10580775B2 (en) 2020-03-03
US9786665B1 (en) 2017-10-10

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