JP2018207109A5 - - Google Patents

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JP2018207109A5
JP2018207109A5 JP2018107506A JP2018107506A JP2018207109A5 JP 2018207109 A5 JP2018207109 A5 JP 2018207109A5 JP 2018107506 A JP2018107506 A JP 2018107506A JP 2018107506 A JP2018107506 A JP 2018107506A JP 2018207109 A5 JP2018207109 A5 JP 2018207109A5
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Japan
Prior art keywords
etching
plasma
main
metal layer
dicing
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JP2018107506A
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Japanese (ja)
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JP2018207109A (ja
JP7042165B2 (ja
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Priority claimed from GBGB1708927.7A external-priority patent/GB201708927D0/en
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JP2018107506A 2017-06-05 2018-06-05 プラズマエッチング方法及びプラズマダイシング方法 Active JP7042165B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1708927.7 2017-06-05
GBGB1708927.7A GB201708927D0 (en) 2017-06-05 2017-06-05 Methods of plasma etching and plasma dicing

Publications (3)

Publication Number Publication Date
JP2018207109A JP2018207109A (ja) 2018-12-27
JP2018207109A5 true JP2018207109A5 (enExample) 2021-07-26
JP7042165B2 JP7042165B2 (ja) 2022-03-25

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JP2018107506A Active JP7042165B2 (ja) 2017-06-05 2018-06-05 プラズマエッチング方法及びプラズマダイシング方法

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US (1) US10872775B2 (enExample)
EP (1) EP3413341B1 (enExample)
JP (1) JP7042165B2 (enExample)
KR (1) KR102364952B1 (enExample)
CN (1) CN108987342B (enExample)
GB (1) GB201708927D0 (enExample)
TW (1) TWI791531B (enExample)

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US11658103B2 (en) * 2020-09-11 2023-05-23 Qualcomm Incorporated Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps
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CN114724948B (zh) * 2022-03-30 2025-11-04 青岛惠科微电子有限公司 硅片的湿法蚀刻方法和装置
US20240071828A1 (en) * 2022-08-31 2024-02-29 Texas Instruments Incorporated Methods of separating semiconductor dies
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