CN108987342B - 等离子体蚀刻和等离子体切割的方法 - Google Patents
等离子体蚀刻和等离子体切割的方法 Download PDFInfo
- Publication number
- CN108987342B CN108987342B CN201810568915.0A CN201810568915A CN108987342B CN 108987342 B CN108987342 B CN 108987342B CN 201810568915 A CN201810568915 A CN 201810568915A CN 108987342 B CN108987342 B CN 108987342B
- Authority
- CN
- China
- Prior art keywords
- etching
- etch
- main
- plasma
- step during
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Dicing (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB1708927.7A GB201708927D0 (en) | 2017-06-05 | 2017-06-05 | Methods of plasma etching and plasma dicing |
| GB1708927.7 | 2017-06-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108987342A CN108987342A (zh) | 2018-12-11 |
| CN108987342B true CN108987342B (zh) | 2023-07-18 |
Family
ID=59350031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810568915.0A Active CN108987342B (zh) | 2017-06-05 | 2018-06-05 | 等离子体蚀刻和等离子体切割的方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10872775B2 (enExample) |
| EP (1) | EP3413341B1 (enExample) |
| JP (1) | JP7042165B2 (enExample) |
| KR (1) | KR102364952B1 (enExample) |
| CN (1) | CN108987342B (enExample) |
| GB (1) | GB201708927D0 (enExample) |
| TW (1) | TWI791531B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10818551B2 (en) * | 2019-01-09 | 2020-10-27 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
| US20210118734A1 (en) * | 2019-10-22 | 2021-04-22 | Semiconductor Components Industries, Llc | Plasma-singulated, contaminant-reduced semiconductor die |
| KR102824210B1 (ko) * | 2019-10-28 | 2025-06-25 | 삼성전자주식회사 | 반도체 소자 및 제조방법 |
| US11721586B2 (en) * | 2019-12-19 | 2023-08-08 | Nxp B.V. | Method and system for regulating plasma dicing rates |
| US11658103B2 (en) * | 2020-09-11 | 2023-05-23 | Qualcomm Incorporated | Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps |
| TWI771893B (zh) * | 2021-02-03 | 2022-07-21 | 國立陽明交通大學 | 陣列式晶片的切割方法 |
| CN114724948B (zh) * | 2022-03-30 | 2025-11-04 | 青岛惠科微电子有限公司 | 硅片的湿法蚀刻方法和装置 |
| US20240071828A1 (en) * | 2022-08-31 | 2024-02-29 | Texas Instruments Incorporated | Methods of separating semiconductor dies |
| US20240258112A1 (en) * | 2023-01-30 | 2024-08-01 | Texas Instruments Incorporated | Multi-loop time varying bosch process for 2-dimensional small cd high aspect ratio deep silicon trench etching |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0691678A2 (en) * | 1994-07-08 | 1996-01-10 | Applied Materials, Inc. | Process for plasma etching of vias in a dielectric layer with removal of residues |
| EP0731501A1 (en) * | 1995-03-08 | 1996-09-11 | International Business Machines Corporation | Method for plasma etching an oxide/polycide structure |
| US5620525A (en) * | 1990-07-16 | 1997-04-15 | Novellus Systems, Inc. | Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate |
| JP2008217384A (ja) * | 2007-03-05 | 2008-09-18 | Hitachi Ltd | 回路チップ及びその製造方法、並びにこれを搭載したrfid回路装置 |
| KR20160029097A (ko) * | 2013-07-02 | 2016-03-14 | 어플라이드 머티어리얼스, 인코포레이티드 | 높은 다이 파괴 강도 및 평활한 측벽을 위한 레이저 스크라이빙 및 플라즈마 에칭 |
| JP2017063145A (ja) * | 2015-09-25 | 2017-03-30 | 三菱電機株式会社 | 炭化珪素半導体装置及びその製造方法 |
| JP2017073439A (ja) * | 2015-10-06 | 2017-04-13 | 株式会社ディスコ | デバイスの製造方法 |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6846746B2 (en) | 2002-05-01 | 2005-01-25 | Applied Materials, Inc. | Method of smoothing a trench sidewall after a deep trench silicon etch process |
| JP4812512B2 (ja) | 2006-05-19 | 2011-11-09 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置の製造方法 |
| DE102007009913B4 (de) * | 2007-02-28 | 2012-10-18 | Advanced Micro Devices, Inc. | Plasmaätzprozess mit hoher Ausbeute für Zwischenschichtdielektrika |
| CN101925983A (zh) * | 2007-12-21 | 2010-12-22 | 苏威氟有限公司 | 用于生产微机电系统的方法 |
| JP2010259160A (ja) | 2009-04-22 | 2010-11-11 | Sumitomo Precision Prod Co Ltd | 発電装置およびシリコン片の製造方法 |
| JP5676941B2 (ja) | 2010-07-06 | 2015-02-25 | キヤノン株式会社 | 配線基板の製造方法及び配線基板 |
| US8871105B2 (en) | 2011-05-12 | 2014-10-28 | Lam Research Corporation | Method for achieving smooth side walls after Bosch etch process |
| US8450188B1 (en) | 2011-08-02 | 2013-05-28 | Micro Processing Technology, Inc. | Method of removing back metal from an etched semiconductor scribe street |
| JP5957926B2 (ja) | 2012-02-09 | 2016-07-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| GB2499816A (en) | 2012-02-29 | 2013-09-04 | Oxford Instr Nanotechnology Tools Ltd | Controlling deposition and etching in a chamber with fine time control of parameters and gas flow |
| US8993414B2 (en) * | 2012-07-13 | 2015-03-31 | Applied Materials, Inc. | Laser scribing and plasma etch for high die break strength and clean sidewall |
| US8664089B1 (en) * | 2012-08-20 | 2014-03-04 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US9034733B2 (en) | 2012-08-20 | 2015-05-19 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
| US9368404B2 (en) | 2012-09-28 | 2016-06-14 | Plasma-Therm Llc | Method for dicing a substrate with back metal |
| US9153493B1 (en) | 2013-01-16 | 2015-10-06 | Micro Processing Technology, Inc. | System for separating devices from a semiconductor wafer |
| US8980726B2 (en) | 2013-01-25 | 2015-03-17 | Applied Materials, Inc. | Substrate dicing by laser ablation and plasma etch damage removal for ultra-thin wafers |
| EP3594998B1 (en) * | 2013-03-06 | 2022-01-05 | Plasma-Therm, Llc | Method for plasma dicing a semi-conductor wafer |
| US9224615B2 (en) * | 2013-09-11 | 2015-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Noble gas bombardment to reduce scallops in bosch etching |
| US8906745B1 (en) | 2013-09-12 | 2014-12-09 | Micro Processing Technology, Inc. | Method using fluid pressure to remove back metal from semiconductor wafer scribe streets |
| US9460966B2 (en) * | 2013-10-10 | 2016-10-04 | Applied Materials, Inc. | Method and apparatus for dicing wafers having thick passivation polymer layer |
| CN104576506A (zh) | 2013-10-22 | 2015-04-29 | 中微半导体设备(上海)有限公司 | 一种刻蚀硅通孔的方法 |
| CN103646917B (zh) * | 2013-11-28 | 2016-04-13 | 中微半导体设备(上海)有限公司 | 硅通孔形成方法 |
| US9312177B2 (en) * | 2013-12-06 | 2016-04-12 | Applied Materials, Inc. | Screen print mask for laser scribe and plasma etch wafer dicing process |
| JP6250429B2 (ja) | 2014-02-13 | 2017-12-20 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置およびその製造方法 |
| US9275902B2 (en) * | 2014-03-26 | 2016-03-01 | Applied Materials, Inc. | Dicing processes for thin wafers with bumps on wafer backside |
| JP2016018838A (ja) | 2014-07-07 | 2016-02-01 | 株式会社リコー | シリコン基板の加工方法 |
| EP3012857A1 (en) * | 2014-10-21 | 2016-04-27 | ams AG | Method of producing an opening with smooth vertical sidewall in a semiconductor substrate |
| JP6476418B2 (ja) * | 2016-02-04 | 2019-03-06 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および電子部品実装構造体の製造方法 |
| JP6476419B2 (ja) * | 2016-02-04 | 2019-03-06 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および素子チップ |
| JP6575874B2 (ja) * | 2016-03-09 | 2019-09-18 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
| JP6604476B2 (ja) * | 2016-03-11 | 2019-11-13 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
| JP2018056502A (ja) * | 2016-09-30 | 2018-04-05 | 株式会社ディスコ | デバイスウエーハの加工方法 |
| JP6524562B2 (ja) * | 2017-02-23 | 2019-06-05 | パナソニックIpマネジメント株式会社 | 素子チップおよびその製造方法 |
-
2017
- 2017-06-05 GB GBGB1708927.7A patent/GB201708927D0/en not_active Ceased
-
2018
- 2018-06-01 US US15/995,184 patent/US10872775B2/en active Active
- 2018-06-04 TW TW107119191A patent/TWI791531B/zh active
- 2018-06-04 KR KR1020180064448A patent/KR102364952B1/ko active Active
- 2018-06-05 JP JP2018107506A patent/JP7042165B2/ja active Active
- 2018-06-05 CN CN201810568915.0A patent/CN108987342B/zh active Active
- 2018-06-05 EP EP18176104.0A patent/EP3413341B1/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5620525A (en) * | 1990-07-16 | 1997-04-15 | Novellus Systems, Inc. | Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate |
| EP0691678A2 (en) * | 1994-07-08 | 1996-01-10 | Applied Materials, Inc. | Process for plasma etching of vias in a dielectric layer with removal of residues |
| EP0731501A1 (en) * | 1995-03-08 | 1996-09-11 | International Business Machines Corporation | Method for plasma etching an oxide/polycide structure |
| JP2008217384A (ja) * | 2007-03-05 | 2008-09-18 | Hitachi Ltd | 回路チップ及びその製造方法、並びにこれを搭載したrfid回路装置 |
| KR20160029097A (ko) * | 2013-07-02 | 2016-03-14 | 어플라이드 머티어리얼스, 인코포레이티드 | 높은 다이 파괴 강도 및 평활한 측벽을 위한 레이저 스크라이빙 및 플라즈마 에칭 |
| JP2017063145A (ja) * | 2015-09-25 | 2017-03-30 | 三菱電機株式会社 | 炭化珪素半導体装置及びその製造方法 |
| JP2017073439A (ja) * | 2015-10-06 | 2017-04-13 | 株式会社ディスコ | デバイスの製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180350615A1 (en) | 2018-12-06 |
| JP2018207109A (ja) | 2018-12-27 |
| CN108987342A (zh) | 2018-12-11 |
| KR102364952B1 (ko) | 2022-02-17 |
| EP3413341A1 (en) | 2018-12-12 |
| TWI791531B (zh) | 2023-02-11 |
| JP7042165B2 (ja) | 2022-03-25 |
| GB201708927D0 (en) | 2017-07-19 |
| TW201903889A (zh) | 2019-01-16 |
| US10872775B2 (en) | 2020-12-22 |
| EP3413341B1 (en) | 2022-04-27 |
| KR20180133231A (ko) | 2018-12-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108987342B (zh) | 等离子体蚀刻和等离子体切割的方法 | |
| CN104465513B (zh) | 半导体器件和用于制造半导体器件的方法 | |
| CN105584986B (zh) | 一种硅深孔刻蚀方法 | |
| JP2005522874A (ja) | 基板をエッチングする方法 | |
| CN1973362A (zh) | 超薄管芯及其制造方法 | |
| JP6387131B2 (ja) | プラズマ加工方法及びこの方法を用いて製造された基板 | |
| JP6441088B2 (ja) | シリコンウェーハの製造方法及び半導体装置の製造方法 | |
| CN108206131A (zh) | 半导体结构以及半导体结构的形成方法 | |
| JP5509057B2 (ja) | 半導体チップの製造方法 | |
| CN105448648A (zh) | 一种晶片流片方法 | |
| CN112701062A (zh) | 等离子体切单的、污染物减少的半导体管芯 | |
| JP2018137483A (ja) | プラズマ加工方法及びこの方法を用いて製造された基板 | |
| JP2008072032A (ja) | 半導体装置の製造方法 | |
| US7179720B2 (en) | Pre-fabrication scribing | |
| TWI810847B (zh) | 磷化銦基板 | |
| CN114171381B (zh) | 一种硬掩模刻蚀图形的方法及制冷红外探测器的制备方法 | |
| US20250062129A1 (en) | DIE BACKSIDE PROFILE for SEMICONDUCTOR DEVICES | |
| CN102881625B (zh) | 隔离结构以及半导体结构的形成方法 | |
| EP4576172A1 (en) | Methods of treating a semiconductor substrate and apparatus | |
| TWI843148B (zh) | 用於矽上gan晶圓之單粒化的系統及方法 | |
| US10056297B1 (en) | Modified plasma dicing process to improve back metal cleaving | |
| JP5201229B2 (ja) | 半導体素子の製造方法 | |
| CN101421838B (zh) | 用于制造集成电路的方法 | |
| CN117790418A (zh) | 一种从晶圆切单得到裸片的方法 | |
| CN108109911A (zh) | 一种形成倾斜的坡面结构的方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |