KR102364952B1 - 플라즈마 에칭 및 플라즈마 다이싱 방법 - Google Patents

플라즈마 에칭 및 플라즈마 다이싱 방법 Download PDF

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KR102364952B1
KR102364952B1 KR1020180064448A KR20180064448A KR102364952B1 KR 102364952 B1 KR102364952 B1 KR 102364952B1 KR 1020180064448 A KR1020180064448 A KR 1020180064448A KR 20180064448 A KR20180064448 A KR 20180064448A KR 102364952 B1 KR102364952 B1 KR 102364952B1
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etch
etching
plasma
main
dicing
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KR20180133231A (ko
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제이 안셀 올리버
하니시넥 마틴
홉킨스 자넷
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에스피티에스 테크놀러지스 리미티드
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • H01L21/30655Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Dicing (AREA)
KR1020180064448A 2017-06-05 2018-06-04 플라즈마 에칭 및 플라즈마 다이싱 방법 Active KR102364952B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1708927.7 2017-06-05
GBGB1708927.7A GB201708927D0 (en) 2017-06-05 2017-06-05 Methods of plasma etching and plasma dicing

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KR20180133231A KR20180133231A (ko) 2018-12-13
KR102364952B1 true KR102364952B1 (ko) 2022-02-17

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US (1) US10872775B2 (enExample)
EP (1) EP3413341B1 (enExample)
JP (1) JP7042165B2 (enExample)
KR (1) KR102364952B1 (enExample)
CN (1) CN108987342B (enExample)
GB (1) GB201708927D0 (enExample)
TW (1) TWI791531B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10818551B2 (en) * 2019-01-09 2020-10-27 Semiconductor Components Industries, Llc Plasma die singulation systems and related methods
US20210118734A1 (en) * 2019-10-22 2021-04-22 Semiconductor Components Industries, Llc Plasma-singulated, contaminant-reduced semiconductor die
KR102824210B1 (ko) * 2019-10-28 2025-06-25 삼성전자주식회사 반도체 소자 및 제조방법
US11721586B2 (en) * 2019-12-19 2023-08-08 Nxp B.V. Method and system for regulating plasma dicing rates
US11658103B2 (en) * 2020-09-11 2023-05-23 Qualcomm Incorporated Capacitor interposer layer (CIL) chiplet design with conformal die edge pattern around bumps
TWI771893B (zh) * 2021-02-03 2022-07-21 國立陽明交通大學 陣列式晶片的切割方法
CN114724948B (zh) * 2022-03-30 2025-11-04 青岛惠科微电子有限公司 硅片的湿法蚀刻方法和装置
US20240071828A1 (en) * 2022-08-31 2024-02-29 Texas Instruments Incorporated Methods of separating semiconductor dies
US20240258112A1 (en) * 2023-01-30 2024-08-01 Texas Instruments Incorporated Multi-loop time varying bosch process for 2-dimensional small cd high aspect ratio deep silicon trench etching

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646917A (zh) * 2013-11-28 2014-03-19 中微半导体设备(上海)有限公司 硅通孔形成方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620525A (en) * 1990-07-16 1997-04-15 Novellus Systems, Inc. Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate
US5514247A (en) * 1994-07-08 1996-05-07 Applied Materials, Inc. Process for plasma etching of vias
EP0731501A1 (en) * 1995-03-08 1996-09-11 International Business Machines Corporation Method for plasma etching an oxide/polycide structure
US6846746B2 (en) 2002-05-01 2005-01-25 Applied Materials, Inc. Method of smoothing a trench sidewall after a deep trench silicon etch process
JP4812512B2 (ja) * 2006-05-19 2011-11-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
DE102007009913B4 (de) * 2007-02-28 2012-10-18 Advanced Micro Devices, Inc. Plasmaätzprozess mit hoher Ausbeute für Zwischenschichtdielektrika
JP2008217384A (ja) * 2007-03-05 2008-09-18 Hitachi Ltd 回路チップ及びその製造方法、並びにこれを搭載したrfid回路装置
RU2010130570A (ru) * 2007-12-21 2012-01-27 Солвей Флуор Гмбх (De) Способ получения микроэлектромеханических систем
JP2010259160A (ja) * 2009-04-22 2010-11-11 Sumitomo Precision Prod Co Ltd 発電装置およびシリコン片の製造方法
JP5676941B2 (ja) * 2010-07-06 2015-02-25 キヤノン株式会社 配線基板の製造方法及び配線基板
US8871105B2 (en) * 2011-05-12 2014-10-28 Lam Research Corporation Method for achieving smooth side walls after Bosch etch process
US8450188B1 (en) 2011-08-02 2013-05-28 Micro Processing Technology, Inc. Method of removing back metal from an etched semiconductor scribe street
JP5957926B2 (ja) * 2012-02-09 2016-07-27 セイコーエプソン株式会社 半導体装置の製造方法
GB2499816A (en) 2012-02-29 2013-09-04 Oxford Instr Nanotechnology Tools Ltd Controlling deposition and etching in a chamber with fine time control of parameters and gas flow
US8993414B2 (en) * 2012-07-13 2015-03-31 Applied Materials, Inc. Laser scribing and plasma etch for high die break strength and clean sidewall
US9034733B2 (en) 2012-08-20 2015-05-19 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8664089B1 (en) * 2012-08-20 2014-03-04 Semiconductor Components Industries, Llc Semiconductor die singulation method
US9368404B2 (en) 2012-09-28 2016-06-14 Plasma-Therm Llc Method for dicing a substrate with back metal
US9153493B1 (en) 2013-01-16 2015-10-06 Micro Processing Technology, Inc. System for separating devices from a semiconductor wafer
US8980726B2 (en) 2013-01-25 2015-03-17 Applied Materials, Inc. Substrate dicing by laser ablation and plasma etch damage removal for ultra-thin wafers
EP2965349A2 (en) * 2013-03-06 2016-01-13 Plasma-Therm, Llc Method and apparatus for plasma dicing a semi-conductor wafer
US20150011073A1 (en) * 2013-07-02 2015-01-08 Wei-Sheng Lei Laser scribing and plasma etch for high die break strength and smooth sidewall
US9224615B2 (en) * 2013-09-11 2015-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Noble gas bombardment to reduce scallops in bosch etching
US8906745B1 (en) 2013-09-12 2014-12-09 Micro Processing Technology, Inc. Method using fluid pressure to remove back metal from semiconductor wafer scribe streets
US9460966B2 (en) * 2013-10-10 2016-10-04 Applied Materials, Inc. Method and apparatus for dicing wafers having thick passivation polymer layer
CN104576506A (zh) 2013-10-22 2015-04-29 中微半导体设备(上海)有限公司 一种刻蚀硅通孔的方法
US9312177B2 (en) * 2013-12-06 2016-04-12 Applied Materials, Inc. Screen print mask for laser scribe and plasma etch wafer dicing process
JP6250429B2 (ja) * 2014-02-13 2017-12-20 エスアイアイ・セミコンダクタ株式会社 半導体装置およびその製造方法
US9275902B2 (en) * 2014-03-26 2016-03-01 Applied Materials, Inc. Dicing processes for thin wafers with bumps on wafer backside
JP2016018838A (ja) * 2014-07-07 2016-02-01 株式会社リコー シリコン基板の加工方法
EP3012857A1 (en) * 2014-10-21 2016-04-27 ams AG Method of producing an opening with smooth vertical sidewall in a semiconductor substrate
JP6566812B2 (ja) * 2015-09-25 2019-08-28 三菱電機株式会社 炭化珪素半導体装置及びその製造方法
JP6564670B2 (ja) * 2015-10-06 2019-08-21 株式会社ディスコ デバイスの製造方法
JP6476419B2 (ja) * 2016-02-04 2019-03-06 パナソニックIpマネジメント株式会社 素子チップの製造方法および素子チップ
JP6476418B2 (ja) * 2016-02-04 2019-03-06 パナソニックIpマネジメント株式会社 素子チップの製造方法および電子部品実装構造体の製造方法
JP6575874B2 (ja) * 2016-03-09 2019-09-18 パナソニックIpマネジメント株式会社 素子チップの製造方法
JP6604476B2 (ja) * 2016-03-11 2019-11-13 パナソニックIpマネジメント株式会社 素子チップの製造方法
JP2018056502A (ja) * 2016-09-30 2018-04-05 株式会社ディスコ デバイスウエーハの加工方法
JP6524562B2 (ja) * 2017-02-23 2019-06-05 パナソニックIpマネジメント株式会社 素子チップおよびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646917A (zh) * 2013-11-28 2014-03-19 中微半导体设备(上海)有限公司 硅通孔形成方法

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TW201903889A (zh) 2019-01-16
US10872775B2 (en) 2020-12-22
GB201708927D0 (en) 2017-07-19
US20180350615A1 (en) 2018-12-06
EP3413341B1 (en) 2022-04-27
CN108987342A (zh) 2018-12-11
JP2018207109A (ja) 2018-12-27
EP3413341A1 (en) 2018-12-12
KR20180133231A (ko) 2018-12-13
JP7042165B2 (ja) 2022-03-25
CN108987342B (zh) 2023-07-18
TWI791531B (zh) 2023-02-11

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