JP2018085480A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2018085480A JP2018085480A JP2016229032A JP2016229032A JP2018085480A JP 2018085480 A JP2018085480 A JP 2018085480A JP 2016229032 A JP2016229032 A JP 2016229032A JP 2016229032 A JP2016229032 A JP 2016229032A JP 2018085480 A JP2018085480 A JP 2018085480A
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- Prior art keywords
- plating layer
- semiconductor device
- bonding material
- die pad
- sealing portion
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Abstract
【解決手段】半導体装置PKGは、半導体チップCPと、ダイパッドDPと、複数のリードLDと、封止部MRとを備えている。ダイパッドDPおよび複数のリードLDは、銅を主成分とする金属材料からなる。ダイパッドDPの上面には、銀めっき層、金めっき層、または白金めっき層からなるめっき層PL1が形成されている。半導体チップCPは、ダイパッドDPの上面のめっき層PL1上に、接合材BDを介して搭載されており、めっき層PL1は、封止部MRと接触しないように、接合材BDで覆われている。
【選択図】図7
Description
本発明の一実施の形態の半導体装置を図面を参照して説明する。
図1は、本発明の一実施の形態である半導体装置PKGの上面図であり、図2は、半導体装置PKGの下面図(裏面図)であり、図3〜図6は、半導体装置PKGの平面透視図であり、図7は、半導体装置PKGの断面図であり、図8は、半導体装置PKGの一部を拡大した平面透視図(部分拡大平面透視図)である。
次に、上記図1〜図8に示される半導体装置PKGの製造工程(組立工程)について説明する。図9は、上記図1〜図8に示される半導体装置PKGの製造工程を示すプロセスフロー図である。図10〜図18は、半導体装置PKGの製造工程中の平面図または断面図である。図10〜図18のうち、図10、図12、図14および図16が平面図であり、図11、図13、図15、図17および図18が断面図であり、断面図としては、上記図7に相当する断面が示されている。
図19は、本発明者が検討した第1検討例の半導体装置(半導体パッケージ)PKG101の断面図であり、上記図7に相当する断面図が示されている。
本実施の形態の半導体装置PKGは、半導体チップCPと、半導体チップCPを搭載するチップ搭載部であるダイパッドDPと、複数のリードLDと、半導体チップCP、ダイパッドDPの少なくとも一部および複数のリードLDの少なくとも一部を封止する封止部MR(封止体)と、備えている。ダイパッドDPおよび複数のリードLDは、銅を主成分とする金属材料からなる。ダイパッドDPの上面DPaにはめっき層PL1が形成されており、めっき層PL1は、銀めっき層、金めっき層、または白金めっき層からなる。半導体チップCPは、ダイパッドDPの上面DPaのめっき層PL1上に接合材BD(第1接合材)を介して搭載されている。めっき層PL1は、封止部MRと接触しないように、接合材BDで覆われている。
封止部MRの密着性が相対的に低い箇所があれば、その箇所が起点となって封止部MRの剥離が進行する虞がある。このため、封止部MRの剥離を防ぐには、封止部MRの密着性が相対的に低い箇所があれば、それに対して対策を施すことが有効である。本実施の形態では、めっき層PL1全体を接合材BDで覆うことで、めっき層PL1と封止部MRとが接触しないようにしているため、めっき層PL1と封止部MRとの密着性を気にする必要はない。また、上述のように、接合材BDとして、導電性材料(好ましくは銀粒子のような金属粒子)と樹脂材料とを含有する導電性接合材を用いるか、あるいは、焼結金属(好ましくは焼結銀)を用いることにより、接合材BDと封止部MRとの密着性を高くすることができる。このため、封止部MRの剥離を防ぐためのめっき層PL1と接合材BDとに対する対策は施されている。従って、めっき層PL1が形成されていない領域のダイパッドDPの表面と封止部MRとの密着性を向上できれば、封止部MRの剥離を防ぐ効果は、更に高まることになる。
BW ワイヤ
CC 回路形成領域
CP 半導体チップ
DP,DP101,DP201 ダイパッド
DPa 上面
DPb 下面
LD リード
LF リードフレーム
MR 封止部
MRa 上面
MRb 下面
PD パッド電極
PKG,PKG1,PKG101,PKG201 半導体装置
PL1,PL1a,PL2,PL201 めっき層
TL 吊りリード
Claims (20)
- 半導体チップと、
前記半導体チップを搭載する主面、および前記主面と反対側の裏面を有するチップ搭載部と、
複数のリードと、
前記半導体チップ、前記チップ搭載部の少なくとも一部、および前記複数のリードの少なくとも一部、を封止する封止体と、
を備える半導体装置であって、
前記チップ搭載部および前記複数のリードは、銅を主成分とする金属材料からなり、
前記チップ搭載部の前記主面には、めっき層が形成され、
前記めっき層は、銀めっき層、金めっき層、または白金めっき層からなり、
前記半導体チップは、前記チップ搭載部の前記主面の前記めっき層上に、第1接合材を介して搭載されており、
前記めっき層は、前記封止体と接触しないように、前記第1接合材で覆われている、半導体装置。 - 請求項1記載の半導体装置において、
平面視において、前記めっき層は前記半導体チップに内包されている、半導体装置。 - 請求項2記載の半導体装置において、
前記めっき層の面積は、前記半導体チップの面積の70%以上である、半導体装置。 - 請求項2記載の半導体装置において、
平面視において、前記半導体チップにおける回路形成領域は、前記めっき層に内包されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接合材は、導電性材料と樹脂材料とを含有する導電性接合材からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記第1接合材は、焼結金属からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記チップ搭載部の前記裏面は、前記封止体から露出されている、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体チップの複数のパッド電極と前記複数のリードとを電気的に接続する複数のワイヤを更に有し、
前記封止体は、前記複数のワイヤを封止している、半導体装置。 - 請求項1記載の半導体装置において、
前記チップ搭載部の前記主面のうち、前記めっき層が形成されていない第1領域の表面粗さは、前記めっき層の表面粗さよりも粗い、半導体装置。 - 請求項9記載の半導体装置において、
前記チップ搭載部の前記主面のうち、前記めっき層が形成されていない前記第1領域の表面粗さは、前記複数のリードのうち、前記封止体から露出する第2領域の表面粗さよりも粗い、半導体装置。 - 請求項1記載の半導体装置において、
前記チップ搭載部の前記封止体接する領域は、粗面化されている、半導体装置。 - 請求項1記載の半導体装置において、
前記めっき層は銀めっき層である、半導体装置。 - (a)めっき層が形成された主面を有するチップ搭載部と、複数のリードと、を有するリードフレームを準備する工程、
(b)前記リードフレームの前記チップ搭載部の前記主面の前記めっき層上に、接合材を介して半導体チップを搭載する工程、
(c)前記接合材を硬化させる工程、
(d)前記半導体チップと前記チップ搭載部の少なくとも一部と前記複数のリードの少なくとも一部とを封止する封止体を形成する工程、
を有する半導体装置の製造方法であって、
前記(a)工程で準備された前記リードフレームは、銅を主成分とする金属材料からなり、
前記めっき層は、銀めっき層、金めっき層、または白金めっき層からなり、
前記(b)工程では、前記接合材は導電性材料と樹脂材料とを含有しており、前記半導体チップを搭載すると、前記めっき層は、前記めっき層が露出しないように、前記接合材で覆われる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(b)工程後で、前記(c)工程前に、
(b1)前記半導体チップの複数のパッド電極と前記複数のリードとを複数のワイヤを介して電気的に接続する工程、
を更に有し、
前記封止体は、前記複数のワイヤも封止する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(b)工程で搭載された前記半導体チップは、平面視において、前記めっき層を内包している、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記めっき層の面積は、前記半導体チップの面積の70%以上である、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(c)工程では、前記接合材は、前記導電性材料として複数の銀粒子を含有している、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記チップ搭載部の前記主面とは反対側の裏面は、前記封止体から露出される、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記めっき層は、銀めっき層である、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(a)工程で準備された前記リードフレームにおいて、前記チップ搭載部のうち、前記封止体で覆われる予定領域は、粗面化されている、半導体装置の製造方法。
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WO2021182047A1 (ja) * | 2020-03-11 | 2021-09-16 | ローム株式会社 | 半導体装置 |
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US10763195B2 (en) * | 2018-03-23 | 2020-09-01 | Stmicroelectronics S.R.L. | Leadframe package using selectively pre-plated leadframe |
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