JP2017168683A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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JP2017168683A
JP2017168683A JP2016053127A JP2016053127A JP2017168683A JP 2017168683 A JP2017168683 A JP 2017168683A JP 2016053127 A JP2016053127 A JP 2016053127A JP 2016053127 A JP2016053127 A JP 2016053127A JP 2017168683 A JP2017168683 A JP 2017168683A
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semiconductor device
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JP6756125B2 (ja
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智紀 片野
Tomonori Katano
智紀 片野
文一 今井
Fumikazu Imai
文一 今井
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

【課題】半導体基板上にキャリア濃度が異なる領域を容易に形成できること。
【解決手段】第１導電型の半導体基板１の表面に、第２導電型の不純物を選択的にドープしてドープ領域４１，４２を形成し、ドープ領域４１，４２の表面の一部を断熱膜７で被覆し、少なくともドープ領域の表面の残りを吸収膜８２で被覆し、吸収膜８２を介してドープ領域４１，４２を加熱することで、第２導電型の不純物領域が同じ不純物濃度でキャリア濃度が互いに異なる２つ以上のドープ領域４１，４２を形成できる。
【選択図】図２

Description

この発明は、シリコンあるいはワイドバンドギャップの半導体材料を用いた半導体装置および半導体装置の製造方法に関する。
パワーデバイスなどの半導体装置では、素子の耐圧レベルを確保するため、その活性領域外周のｐ+領域からチャージレベルを外周方向に向かって段階的に小さくするＪＴＥ（Ｊｕｎｃｔｉｏｎ Ｔｅｒｍｉｎａｔｉｏｎ Ｅｘｔｅｎｓｉｏｎ）と呼ばれるエッジ構造、が多く採用される（例えば、下記特許文献１参照。）。
また、第１導電型の半導体基板の表面又は裏面に選択的に第２導電型領域を形成し、この第２導電型領域の不純物濃度を変えることによって、半導体装置が形成される。ＪＴＥ領域ではチャージレベルをコントロールするため、半導体基板上でキャリア濃度を段階的に小さくする。
図４は、従来のＪＴＥ構造の断面図である。ショットキーバリアダイオードを例に説明する。例えばＳｉＣ（炭化珪素）などの材料であるｎ+半導体基板１上にはエピタキシャル成長によるドリフト層であるｎ-領域２が形成される。さらに、ｎ-領域２の上には例えばアルミニウム（Ａｌ）などが注入された活性部ｐ+領域３が形成され、この上には例えばチタン（Ｔｉ）などのショットキーメタル５が設けられる。
ｐ+領域３の外周には、キャリア濃度が薄いｐ領域４１が形成され、そのさらに外周にはさらに濃度が薄いｐ-領域４２が形成される。このような構成により、逆方向の電圧が印加された際、エッジ構造に生じる電界集中を緩和させ、必要な耐圧レベルが確保できる。
図５は、従来のＪＴＥ空間変調構造の断面図である。ｐ領域４１と、ｐ-領域４２の比率を段階的に変えながら分散させることで、より電界集中の度合いを緩和し、耐圧レベルをさらに改善できる。このようなエッジ構造は、ショットキーバリアダイオードばかりでなく、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）やＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）等のＭＯＳ型パワーデバイスでも用いられる技術である。
特表２００１−５０８９５０号公報
しかし、上述したＪＴＥ構造を構成するには、キャリア濃度の異なる領域それぞれについて不純物を注入する作業を繰り返さなければならない。さらに、ＳｉＣのように不純物が熱拡散しにくい材料では、深さ方向に最適な濃度分布を得るため、一つの領域でもエネルギーを変えながら何度も注入作業を繰り返す必要がある。
このため、注入工程に要する工数が非常に多くなる、あるいは不純物注入装置への過重負担により、製造装置全体の稼働率が低下して製品のコストが上がる等の問題が生じていた。
本発明は、半導体基板上にキャリア濃度が異なる領域を容易に形成できることを目的とする。
上述した課題を解決し、本発明の目的を達成するために、この発明にかかる半導体装置は、第１導電型の半導体基板の表面に、第２導電型の不純物領域が選択的に設けられた半導体装置において、前記第２導電型の不純物領域が同じ不純物濃度でキャリア濃度が互いに異なる２つ以上の複数領域を有することを特徴とする。
また、この発明にかかる半導体装置は、上述した発明において、前記複数領域の不純物の活性化率が領域ごとに異なることを特徴とする。
また、この発明にかかる半導体装置は、上述した発明において、半導体装置構造として、活性領域と、当該活性領域を取り囲むエッジ領域を備え、前記複数領域が前記エッジ領域の耐圧構造として設けられていることを特徴とする。
また、この発明にかかる半導体装置は、上述した発明において、前記半導体基板が炭化シリコン、窒化ガリウム、シリコン、ダイアモンドのいずれか１つであることを特徴とする。
また、この発明にかかる半導体装置の製造方法は、第１導電型の半導体基板の表面に、第２導電型の不純物領域を選択的に形成する半導体装置の製造方法であって、前記半導体基板の表面に第２導電型の不純物を選択的にドープしてドープ領域を形成する工程と、前記ドープ領域の表面の一部を断熱膜で被覆する工程と、さらに、少なくとも前記ドープ領域の表面の残りを吸収膜で被覆する工程と、前記吸収膜を介して前記ドープ領域を加熱する工程と、を含むことを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記吸収膜として、光のエネルギーを１０％以上吸収する膜を用いることを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記吸収膜として、カーボンを用いることを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記加熱する工程では、光加熱を行うことを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記加熱する工程では、光源として、ハロゲンランプ、エキシマランプ、ＹＡＧレーザ、エキシマレーザ、ＣＯ2レーザ、半導体レーザ、のいずれか１つを用いることを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記断熱膜として、熱伝導率が５０Ｗ／ｍ・Ｋ以下のものを用いることを特徴とする。
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記断熱膜として、窒化珪素、もしくは酸化珪素の材料を用いることを特徴とする。
上述した発明によれば、半導体基板上にキャリア濃度が異なる領域を形成するために、領域ごとに異なる濃度の不純物注入を繰り返す必要がなく、共通濃度で不純物注入を行い、領域ごとに活性化のための加熱温度を異にして活性化率を制御することで異なるキャリア濃度の領域を形成できる。これにより、工数負担が大きい不純物注入工程を減らすことができ、製品がコストアップせず、簡単に製造できるようになる。
本発明によれば、半導体基板上にキャリア濃度が異なる領域を容易に形成できるという効果を奏する。
図１は、一般的なＪＴＥ構造形成時の加熱処理を説明する断面図である。 図２は、本発明の実施の形態１にかかるＪＴＥ構造形成時の状態を示す断面図である。 図３は、本発明の実施の形態２にかかるＪＴＥ構造形成時の状態を示す断面図である。 図４は、従来のＪＴＥ構造の断面図である。 図５は、従来のＪＴＥ空間変調構造の断面図である。
（実施の形態１）
以下に添付図面を参照して、この発明の好適な実施の形態を詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および−は、それぞれそれが付されていない層や領域よりも高不純物濃度および低不純物濃度であることを意味する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。なお、本明細書では、ミラー指数の表記において、“−”はその直後の指数につくバーを意味しており、指数の前に“−”を付けることで負の指数を表している。
はじめに、一般的なショットキーバリアダイオードにおけるＪＴＥ構造の形成方法についてまず説明しておく。
一般的なショットキーバリアダイオード（図４参照）において、半導体基板１がＳｉＣなどの材料の場合、注入したＡｌ等の不純物はそのままではキャリアにはならず、１０００℃以上の加熱処理を行うことで、初めて不純物は半導体基板１の材料構造に取り込まれキャリアになる。この過程を活性化と呼ぶ。
図１は、一般的なＪＴＥ構造形成時の加熱処理を説明する断面図である。図１に示すように、活性部のｐ+領域３、およびＪＴＥのｐ領域４１、ｐ-領域４２にそれぞれ異なる濃度の不純物を注入する。その後、高周波誘導加熱などで基板ステージ６を加熱し、基板ステージ６からの熱伝導もしくは輻射により、半導体基板１を加熱し、活性部のｐ+領域３、およびＪＴＥのｐ領域４１、ｐ-領域４２を活性化させる。
なおこの際、加熱処理により半導体基板１の板面（主面）が荒れないように、予めキャップ膜８１で被覆しておき、加熱処理終了後にキャップ膜８１を除去する。
図２は、本発明の実施の形態１にかかるＪＴＥ構造形成時の状態を示す断面図である。実施の形態１では、図２に示すように、第１導電体の材料からなる半導体基板１上に選択的に形成しようとする活性部のｐ+領域３および、ＪＴＥのｐ領域４１、４２（領域４２は後述するがｐ−領域となる）にＡｌ等の不純物を注入する。このとき領域４１および４２は共通の不純物濃度とする。半導体基板１は、炭化シリコン、窒化ガリウム、シリコン、ダイアモンドのいずれかを用いる。
その後、半導体基板１上のｐ領域４２の部分には、熱伝導率が小さく断熱性のある、具体的には熱伝導率が５０Ｗ／ｍ・Ｋ以下の例えば、窒化珪素、酸化珪素等よりなる断熱膜７を形成する。
続いて、光エネルギーを吸収し発熱する、例えばカーボン等の吸収膜８２を、領域３、領域４１、領域４２（第２導電体の材料からなるｐ+領域３、ｐ領域４１、ｐ領域４２となる部分）を被覆するように形成する。ここで、後段の加熱として基板ステージからの熱伝導を用いる場合、光エネルギーを吸収する機能は吸収膜８２に必要なく、熱伝導の良い材料であればよい。
次に、吸収膜８２を加熱し、吸収膜８２からの熱流束により注入した不純物を活性化する。具体的には、吸収膜８２に、例えばハロゲンランプ、エキシマランプ等の光源、あるいはＹＡＧ、エキシマ、ＣＯ2、半導体等のレーザ光源を用いた加熱光９を照射する。吸収膜８２は加熱光９のエネルギーを吸収、発熱する。ここで、加熱方法は、吸収膜８２への加熱であれば何でもよく、例えば基板ステージからの熱伝導や輻射を用いても良い。ここで、熱伝導による加熱の場合、面内均一性を確保するためには基板ステージと吸収膜８２とを均一に密着させる必要がある。これに対し、加熱光など輻射を用いる場合、基板の表面形状にかかわらず均一性を確保できる利点がある。
加熱光を用いる場合、吸収膜８２は加熱光９の光エネルギーによって領域３、領域４１、領域４２に対し十分な加熱温度を与えられるよう（領域３、領域４１、領域４２部分で加熱光９の光エネルギーが少なくとも１０％以上吸収できるように）、吸収膜８２の材料の吸収係数、膜厚を設定する。
吸収膜８２からの熱流束８ｈ１により、領域３、領域４１は加熱され、領域３、領域４１は従来と同様に活性化されて、それぞれｐ+、ｐ領域になる（ｐ+領域３、ｐ領域４１）。
一方、領域４２では断熱膜７により熱流束８ｈ１よりも小さい８ｈ２が与えられるので、領域４１よりも低い加熱温度となる。注入した不純物がキャリアに活性化される割合は加熱温度に依存し、低い加熱温度では活性化される割合が低く、領域４２は領域４１よりも低いキャリア濃度となる（ｐ-領域４２）。
従って断熱膜７の材質、膜厚、加熱光の照射条件などを最適化すれば、ＪＴＥ構造のｐ-領域４２に相当するキャリア濃度を与えることができる。断熱膜７は、膜の熱伝導率は５０Ｗ／ｍ・Ｋ以下が望ましく、窒化珪素、酸化珪素などが適用できる。例えば、断熱膜７を０．３μｍ程度の厚さとした上で、領域４１が１７００℃程度になる条件で加熱光を照射すれば良い。
領域４１と４２の不純物濃度を２．５×１０13ｃｍ-2としたとき、領域４１の活性化率４０％に対して、領域４２の活性化率が２０％とすれば、キャリア濃度は領域４１で１．０×１０13ｃｍ-2、領域４２で０．５×１０13ｃｍ-2となる。
（実施の形態２）
図３は、本発明の実施の形態２にかかるＪＴＥ構造形成時の状態を示す断面図である。実施の形態２では、実施の形態１に比して、さらに電界集中の度合いを緩和し耐圧レベルを上げるＪＴＥ構造の例について説明する。
図３に示すように、実施の形態２では、ＪＴＥをｐ領域４１、ｐ-領域４２、ｐ--領域４３の３つの領域から構成した例である。
実施の形態２では、半導体基板１上に断熱膜７１と断熱膜７２を組み合わせて形成し、領域４２部分の断熱膜７１と、領域４３部分の断熱膜７２の断熱膜厚を変えている。図３の構成例では、領域４２，４３上に断熱膜７１を形成し、断熱膜７１上において領域４３部分にさらに断熱膜７２を形成している。
領域４２、４３の断熱膜７１，７２の膜厚は、例えば、それぞれ０．３μｍと、０．５μｍとすればよい。これにより、領域４３ではより高い断熱効果により、もう一段低い加熱温度となり、ｐ--領域に相当するキャリア濃度が得られる。
以上説明した各実施の形態では吸収膜と不純物領域との間に断熱膜を介した例を説明した。このような断熱膜を形成するに限らず、領域（例えば、領域４１，４２，４３）ごとに吸収膜８２へ照射する加熱光の強度、照射時間に直接差異を付けることでも同様の作用効果を得ることができる。
例えば、レーザ光源により吸収膜８２面内でレーザ光を掃引して加熱する場合、領域ごとにり掃引速度、掃引頻度に変化をつけることにより、各領域ごとに加熱温度が制御できる。
以上のように、本発明の実施の形態によれば、ＪＴＥ領域の形成にかかる不純物注入の工数を減らすことができ、従来生じていた製品コストアップの問題を解消できるようになる。
また、以上の説明では、ショットキーバリアダイオードのエッジ構造の形成について説明したが、これに限らず、活性領域がＭＯＳＦＥＴやＩＧＢＴ等の縦型のＭＯＳ型構造であっても同様に適用することができ、また、ＭＯＳＦＥＴやＩＧＢＴの裏面構造についても同様に適用することができる。
このほか、１チップに縦型のＭＯＳＦＥＴと縦型のショットキーバリアダイオードを並べて集積した構造において、半導体基板の裏面側のキャリア濃度を部分的に変えたい場合においても適用できる。さらには、ＩＧＢＴとダイオードを並べて集積したＲＣ−ＩＧＢＴの裏面側領域の形成にも適用できる。
そして、上記の実施の形態では、ＳｉＣの半導体基板の場合を実施例としたが、これに限らず、シリコンやＧａＮ等の半導体基板であっても実現できる。
以上のように、本発明は半導体材料としてシリコンやワイドバンドギャップを用いる半導体素子に好適であり、例えば、インバータやスイッチング電源等に有用である。
１ 半導体基板
２ ドリフト層
３ ｐ+領域
５ ショットキーメタル
６ 基板ステージ
７ 断熱膜
９ 加熱光
４１ ｐ領域
４２ ｐ-領域
８１ キャップ膜
８２ 吸収膜
８ｈ１，８ｈ２ 熱流束

Claims (11)

  1. 第１導電型の半導体基板の表面に、第２導電型の不純物領域が選択的に設けられた半導体装置において、
    前記第２導電型の不純物領域が同じ不純物濃度でキャリア濃度が互いに異なる２つ以上の複数領域を有することを特徴とする半導体装置。
  2. 前記複数領域の不純物の活性化率が領域ごとに異なることを特徴とする請求項１に記載の半導体装置。
  3. 半導体装置構造として、活性領域と、当該活性領域を取り囲むエッジ領域を備え、
    前記複数領域が前記エッジ領域の耐圧構造として設けられていることを特徴とする請求項１または２に記載の半導体装置。
  4. 前記半導体基板が炭化シリコン、窒化ガリウム、シリコン、ダイアモンドのいずれか１つであることを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。
  5. 第１導電型の半導体基板の表面に、第２導電型の不純物領域を選択的に形成する半導体装置の製造方法であって、
    前記半導体基板の表面に第２導電型の不純物を選択的にドープしてドープ領域を形成する工程と、
    前記ドープ領域の表面の一部を断熱膜で被覆する工程と、
    さらに、少なくとも前記ドープ領域の表面の残りを吸収膜で被覆する工程と、
    前記吸収膜を介して前記ドープ領域を加熱する工程と、
    を含むことを特徴とする半導体装置の製造方法。
  6. 前記吸収膜として、光のエネルギーを１０％以上吸収する膜を用いることを特徴とする請求項５に記載の半導体装置の製造方法。
  7. 前記吸収膜として、カーボンを用いることを特徴とする請求項５または６に記載の半導体装置の製造方法。
  8. 前記加熱する工程では、光加熱を行うことを特徴とする請求項５〜７のいずれか一つに記載の半導体装置の製造方法。
  9. 前記加熱する工程では、光源として、ハロゲンランプ、エキシマランプ、ＹＡＧレーザ、エキシマレーザ、ＣＯ2レーザ、半導体レーザ、のいずれか１つを用いることを特徴とする請求項５〜８のいずれか一つに記載の半導体装置の製造方法。
  10. 前記断熱膜として、熱伝導率が５０Ｗ／ｍ・Ｋ以下のものを用いることを特徴とする請求項５〜９のいずれか一つに記載の半導体装置の製造方法。
  11. 前記断熱膜として、窒化珪素、もしくは酸化珪素の材料を用いることを特徴とする請求項５〜１０のいずれか一つに記載の半導体装置の製造方法。
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