JP2017085120A5 - - Google Patents

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JP2017085120A5
JP2017085120A5 JP2016234984A JP2016234984A JP2017085120A5 JP 2017085120 A5 JP2017085120 A5 JP 2017085120A5 JP 2016234984 A JP2016234984 A JP 2016234984A JP 2016234984 A JP2016234984 A JP 2016234984A JP 2017085120 A5 JP2017085120 A5 JP 2017085120A5
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hierarchy
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sram cell
register file
integrated circuit
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JP2016234984A 2013-03-15 2016-12-02 集積回路の異なる階層上の、読取／書込ポートおよびアクセスロジックを有する３ｄメモリセル Pending JP2017085120A (ja)

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US201361800220P 2013-03-15 2013-03-15
US61/800,220 2013-03-15
US13/939,274 US9171608B2 (en) 2013-03-15 2013-07-11 Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
US13/939,274 2013-07-11

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JP2016501104A Division JP6309608B2 (ja) 2013-03-15 2014-03-11 集積回路の異なる階層上の、読取／書込ポートおよびアクセスロジックを有する３ｄメモリセル

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JP2017085120A JP2017085120A (ja) 2017-05-18
JP2017085120A5 true JP2017085120A5 (enExample) 2017-06-29

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JP2016501104A Expired - Fee Related JP6309608B2 (ja) 2013-03-15 2014-03-11 集積回路の異なる階層上の、読取／書込ポートおよびアクセスロジックを有する３ｄメモリセル
JP2016234984A Pending JP2017085120A (ja) 2013-03-15 2016-12-02 集積回路の異なる階層上の、読取／書込ポートおよびアクセスロジックを有する３ｄメモリセル

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US (2) US9171608B2 (enExample)
EP (1) EP2973706B1 (enExample)
JP (2) JP6309608B2 (enExample)
KR (2) KR20170000397A (enExample)
CN (1) CN105144381B (enExample)
WO (1) WO2014150317A1 (enExample)

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