JP2016514316A5 - - Google Patents
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- Publication number
- JP2016514316A5 JP2016514316A5 JP2015561679A JP2015561679A JP2016514316A5 JP 2016514316 A5 JP2016514316 A5 JP 2016514316A5 JP 2015561679 A JP2015561679 A JP 2015561679A JP 2015561679 A JP2015561679 A JP 2015561679A JP 2016514316 A5 JP2016514316 A5 JP 2016514316A5
- Authority
- JP
- Japan
- Prior art keywords
- logic means
- termination
- signal
- data bus
- bidirectional data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002457 bidirectional effect Effects 0.000 claims 12
- 230000005540 biological transmission Effects 0.000 claims 6
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/787,926 US9088445B2 (en) | 2013-03-07 | 2013-03-07 | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
| US13/787,926 | 2013-03-07 | ||
| PCT/US2014/021401 WO2014138477A1 (en) | 2013-03-07 | 2014-03-06 | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016514316A JP2016514316A (ja) | 2016-05-19 |
| JP2016514316A5 true JP2016514316A5 (enExample) | 2017-03-23 |
| JP6158960B2 JP6158960B2 (ja) | 2017-07-05 |
Family
ID=50442620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015561679A Expired - Fee Related JP6158960B2 (ja) | 2013-03-07 | 2014-03-06 | 双方向バス上の信号をバス速度に基づいて選択的に終端するための方法および装置 |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US9088445B2 (enExample) |
| EP (1) | EP2965217B1 (enExample) |
| JP (1) | JP6158960B2 (enExample) |
| KR (1) | KR101742763B1 (enExample) |
| CN (1) | CN105190584B (enExample) |
| HR (1) | HRP20170912T1 (enExample) |
| RS (1) | RS56030B1 (enExample) |
| SM (1) | SMT201700382T1 (enExample) |
| WO (1) | WO2014138477A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9088445B2 (en) * | 2013-03-07 | 2015-07-21 | Qualcomm Incorporated | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
| US9542305B2 (en) * | 2015-01-16 | 2017-01-10 | Harman International Industries, Inc. | Impedance matching for high speed signaling in memory system |
| TWI705666B (zh) * | 2015-06-15 | 2020-09-21 | 日商新力股份有限公司 | 傳送裝置、接收裝置、通信系統 |
| US9910482B2 (en) * | 2015-09-24 | 2018-03-06 | Qualcomm Incorporated | Memory interface with adjustable voltage and termination and methods of use |
| KR102529187B1 (ko) * | 2016-03-31 | 2023-05-04 | 삼성전자주식회사 | 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템 |
| US9825730B1 (en) * | 2016-09-26 | 2017-11-21 | Dell Products, Lp | System and method for optimizing link performance with lanes operating at different speeds |
| WO2022064548A1 (ja) | 2020-09-23 | 2022-03-31 | キオクシア株式会社 | 半導体記憶装置及びメモリシステム |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5467455A (en) | 1993-11-03 | 1995-11-14 | Motorola, Inc. | Data processing system and method for performing dynamic bus termination |
| JPH1020974A (ja) * | 1996-07-03 | 1998-01-23 | Fujitsu Ltd | バス構造及び入出力バッファ |
| US6557066B1 (en) * | 1999-05-25 | 2003-04-29 | Lsi Logic Corporation | Method and apparatus for data dependent, dual level output driver |
| JP3651410B2 (ja) * | 2001-05-14 | 2005-05-25 | セイコーエプソン株式会社 | 送信回路、データ転送制御装置及び電子機器 |
| JP3756818B2 (ja) * | 2002-01-09 | 2006-03-15 | 株式会社メガチップス | メモリ制御回路および制御システム |
| US6894691B2 (en) | 2002-05-01 | 2005-05-17 | Dell Products L.P. | Dynamic switching of parallel termination for power management with DDR memory |
| KR101019935B1 (ko) * | 2004-03-24 | 2011-03-09 | 퀄컴 인코포레이티드 | 고 데이터 레이트 인터페이스 장치 및 방법 |
| US7173450B2 (en) * | 2004-06-01 | 2007-02-06 | Hewlett-Packard Development Company, L.P. | Bus controller |
| KR100670702B1 (ko) | 2004-10-30 | 2007-01-17 | 주식회사 하이닉스반도체 | 온다이 터미네이션 회로를 구비한 반도체 메모리 장치 |
| KR100801033B1 (ko) * | 2005-11-03 | 2008-02-04 | 삼성전자주식회사 | 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법 |
| JP4615461B2 (ja) * | 2006-03-10 | 2011-01-19 | 京セラミタ株式会社 | メモリコントローラ |
| KR100790821B1 (ko) | 2006-11-15 | 2008-01-03 | 삼성전자주식회사 | 반도체 메모리 장치에서의 온다이 터미네이션 회로 |
| US7864183B1 (en) | 2007-03-08 | 2011-01-04 | Nvidia Corporation | Dynamic switching of memory termination characteristics in a graphics system |
| US7746098B2 (en) | 2008-03-10 | 2010-06-29 | Qimonda North America Corp. | Termination switching based on data rate |
| KR101039862B1 (ko) * | 2008-11-11 | 2011-06-13 | 주식회사 하이닉스반도체 | 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법 |
| KR100980417B1 (ko) * | 2008-12-09 | 2010-09-07 | 주식회사 하이닉스반도체 | 데이터 드라이버 |
| KR100980425B1 (ko) | 2008-12-30 | 2010-09-07 | 주식회사 하이닉스반도체 | 글로벌 입출력 라인 터미네이션 제어 회로 |
| KR101789077B1 (ko) * | 2010-02-23 | 2017-11-20 | 삼성전자주식회사 | 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법 |
| US8274308B2 (en) | 2010-06-28 | 2012-09-25 | Intel Corporation | Method and apparatus for dynamic memory termination |
| US9088445B2 (en) * | 2013-03-07 | 2015-07-21 | Qualcomm Incorporated | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
-
2013
- 2013-03-07 US US13/787,926 patent/US9088445B2/en active Active
-
2014
- 2014-03-06 SM SM20170382T patent/SMT201700382T1/it unknown
- 2014-03-06 RS RS20170544A patent/RS56030B1/sr unknown
- 2014-03-06 WO PCT/US2014/021401 patent/WO2014138477A1/en not_active Ceased
- 2014-03-06 EP EP14716075.8A patent/EP2965217B1/en active Active
- 2014-03-06 HR HRP20170912TT patent/HRP20170912T1/hr unknown
- 2014-03-06 KR KR1020157027341A patent/KR101742763B1/ko not_active Expired - Fee Related
- 2014-03-06 CN CN201480012111.2A patent/CN105190584B/zh active Active
- 2014-03-06 JP JP2015561679A patent/JP6158960B2/ja not_active Expired - Fee Related
-
2015
- 2015-03-19 US US14/663,303 patent/US9246716B2/en active Active
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