HRP20170912T1 - Postupak i uređaj za selektivnu terminaciju signala na bidirekcijskoj magistrali na osnovu brzine magistrale - Google Patents

Postupak i uređaj za selektivnu terminaciju signala na bidirekcijskoj magistrali na osnovu brzine magistrale

Info

Publication number
HRP20170912T1
HRP20170912T1 HRP20170912TT HRP20170912T HRP20170912T1 HR P20170912 T1 HRP20170912 T1 HR P20170912T1 HR P20170912T T HRP20170912T T HR P20170912TT HR P20170912 T HRP20170912 T HR P20170912T HR P20170912 T1 HRP20170912 T1 HR P20170912T1
Authority
HR
Croatia
Prior art keywords
bus
selectively terminating
terminating signals
speed
bidirectional
Prior art date
Application number
HRP20170912TT
Other languages
English (en)
Inventor
Dexter T. CHUN
Sumeet S. SETHI
John D. Eaton
Vinodh R. Cuppu
Vikram Arora
Vaishnav Srinivas
Muhammad A. Muneer
Isaac D. BERK
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of HRP20170912T1 publication Critical patent/HRP20170912T1/hr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Memory System (AREA)
HRP20170912TT 2013-03-07 2017-06-14 Postupak i uređaj za selektivnu terminaciju signala na bidirekcijskoj magistrali na osnovu brzine magistrale HRP20170912T1 (hr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/787,926 US9088445B2 (en) 2013-03-07 2013-03-07 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
PCT/US2014/021401 WO2014138477A1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
EP14716075.8A EP2965217B1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Publications (1)

Publication Number Publication Date
HRP20170912T1 true HRP20170912T1 (hr) 2017-09-22

Family

ID=50442620

Family Applications (1)

Application Number Title Priority Date Filing Date
HRP20170912TT HRP20170912T1 (hr) 2013-03-07 2017-06-14 Postupak i uređaj za selektivnu terminaciju signala na bidirekcijskoj magistrali na osnovu brzine magistrale

Country Status (8)

Country Link
US (2) US9088445B2 (hr)
EP (1) EP2965217B1 (hr)
JP (1) JP6158960B2 (hr)
KR (1) KR101742763B1 (hr)
CN (1) CN105190584B (hr)
HR (1) HRP20170912T1 (hr)
RS (1) RS56030B1 (hr)
WO (1) WO2014138477A1 (hr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US9542305B2 (en) * 2015-01-16 2017-01-10 Harman International Industries, Inc. Impedance matching for high speed signaling in memory system
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
KR102529187B1 (ko) * 2016-03-31 2023-05-04 삼성전자주식회사 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
US9825730B1 (en) * 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH1020974A (ja) * 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
US6557066B1 (en) * 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
JP3651410B2 (ja) * 2001-05-14 2005-05-25 セイコーエプソン株式会社 送信回路、データ転送制御装置及び電子機器
JP3756818B2 (ja) * 2002-01-09 2006-03-15 株式会社メガチップス メモリ制御回路および制御システム
US6894691B2 (en) 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
EP1735988A1 (en) * 2004-03-24 2006-12-27 Qualcomm, Incorporated High data rate interface apparatus and method
US7173450B2 (en) * 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller
KR100670702B1 (ko) 2004-10-30 2007-01-17 주식회사 하이닉스반도체 온다이 터미네이션 회로를 구비한 반도체 메모리 장치
KR100801033B1 (ko) * 2005-11-03 2008-02-04 삼성전자주식회사 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법
JP4615461B2 (ja) * 2006-03-10 2011-01-19 京セラミタ株式会社 メモリコントローラ
KR100790821B1 (ko) 2006-11-15 2008-01-03 삼성전자주식회사 반도체 메모리 장치에서의 온다이 터미네이션 회로
US7864183B1 (en) 2007-03-08 2011-01-04 Nvidia Corporation Dynamic switching of memory termination characteristics in a graphics system
US7746098B2 (en) 2008-03-10 2010-06-29 Qimonda North America Corp. Termination switching based on data rate
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
KR100980417B1 (ko) * 2008-12-09 2010-09-07 주식회사 하이닉스반도체 데이터 드라이버
KR100980425B1 (ko) 2008-12-30 2010-09-07 주식회사 하이닉스반도체 글로벌 입출력 라인 터미네이션 제어 회로
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
US8274308B2 (en) 2010-06-28 2012-09-25 Intel Corporation Method and apparatus for dynamic memory termination
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Also Published As

Publication number Publication date
EP2965217B1 (en) 2017-04-19
US20140253173A1 (en) 2014-09-11
US20150194959A1 (en) 2015-07-09
JP6158960B2 (ja) 2017-07-05
US9088445B2 (en) 2015-07-21
JP2016514316A (ja) 2016-05-19
RS56030B1 (sr) 2017-09-29
US9246716B2 (en) 2016-01-26
KR101742763B1 (ko) 2017-06-01
KR20150126895A (ko) 2015-11-13
WO2014138477A1 (en) 2014-09-12
CN105190584A (zh) 2015-12-23
CN105190584B (zh) 2018-10-30
EP2965217A1 (en) 2016-01-13

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