JP6158960B2 - 双方向バス上の信号をバス速度に基づいて選択的に終端するための方法および装置 - Google Patents

双方向バス上の信号をバス速度に基づいて選択的に終端するための方法および装置 Download PDF

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JP6158960B2
JP6158960B2 JP2015561679A JP2015561679A JP6158960B2 JP 6158960 B2 JP6158960 B2 JP 6158960B2 JP 2015561679 A JP2015561679 A JP 2015561679A JP 2015561679 A JP2015561679 A JP 2015561679A JP 6158960 B2 JP6158960 B2 JP 6158960B2
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Japan
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termination
logic means
signal
data bus
memory
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JP2015561679A
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Japanese (ja)
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JP2016514316A5 (enExample
JP2016514316A (ja
Inventor
デクスター・ティー・チュン
スミート・エス・セティ
ジョン・ディー・イートン
ヴィノド・アール・クップ
ヴィクラム・アロラ
ヴァイシュナヴ・シュリニヴァス
ムハンマド・エー・ムナー
アイザック・ディー・バーク
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2015561679A 2013-03-07 2014-03-06 双方向バス上の信号をバス速度に基づいて選択的に終端するための方法および装置 Expired - Fee Related JP6158960B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/787,926 US9088445B2 (en) 2013-03-07 2013-03-07 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US13/787,926 2013-03-07
PCT/US2014/021401 WO2014138477A1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Publications (3)

Publication Number Publication Date
JP2016514316A JP2016514316A (ja) 2016-05-19
JP2016514316A5 JP2016514316A5 (enExample) 2017-03-23
JP6158960B2 true JP6158960B2 (ja) 2017-07-05

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JP2015561679A Expired - Fee Related JP6158960B2 (ja) 2013-03-07 2014-03-06 双方向バス上の信号をバス速度に基づいて選択的に終端するための方法および装置

Country Status (9)

Country Link
US (2) US9088445B2 (enExample)
EP (1) EP2965217B1 (enExample)
JP (1) JP6158960B2 (enExample)
KR (1) KR101742763B1 (enExample)
CN (1) CN105190584B (enExample)
HR (1) HRP20170912T1 (enExample)
RS (1) RS56030B1 (enExample)
SM (1) SMT201700382T1 (enExample)
WO (1) WO2014138477A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12298826B2 (en) 2020-09-23 2025-05-13 Kioxia Corporation Semiconductor memory device and memory system

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US9542305B2 (en) * 2015-01-16 2017-01-10 Harman International Industries, Inc. Impedance matching for high speed signaling in memory system
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
KR102529187B1 (ko) * 2016-03-31 2023-05-04 삼성전자주식회사 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
US9825730B1 (en) * 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds

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US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH1020974A (ja) * 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
US6557066B1 (en) * 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
JP3651410B2 (ja) * 2001-05-14 2005-05-25 セイコーエプソン株式会社 送信回路、データ転送制御装置及び電子機器
JP3756818B2 (ja) * 2002-01-09 2006-03-15 株式会社メガチップス メモリ制御回路および制御システム
US6894691B2 (en) 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
AU2005227500B2 (en) * 2004-03-24 2008-12-04 Qualcomm Incorporated High data rate interface apparatus and method
US7173450B2 (en) * 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller
KR100670702B1 (ko) 2004-10-30 2007-01-17 주식회사 하이닉스반도체 온다이 터미네이션 회로를 구비한 반도체 메모리 장치
KR100801033B1 (ko) * 2005-11-03 2008-02-04 삼성전자주식회사 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법
JP4615461B2 (ja) * 2006-03-10 2011-01-19 京セラミタ株式会社 メモリコントローラ
KR100790821B1 (ko) 2006-11-15 2008-01-03 삼성전자주식회사 반도체 메모리 장치에서의 온다이 터미네이션 회로
US7864183B1 (en) 2007-03-08 2011-01-04 Nvidia Corporation Dynamic switching of memory termination characteristics in a graphics system
US7746098B2 (en) 2008-03-10 2010-06-29 Qimonda North America Corp. Termination switching based on data rate
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
KR100980417B1 (ko) * 2008-12-09 2010-09-07 주식회사 하이닉스반도체 데이터 드라이버
KR100980425B1 (ko) 2008-12-30 2010-09-07 주식회사 하이닉스반도체 글로벌 입출력 라인 터미네이션 제어 회로
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
US8274308B2 (en) 2010-06-28 2012-09-25 Intel Corporation Method and apparatus for dynamic memory termination
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12298826B2 (en) 2020-09-23 2025-05-13 Kioxia Corporation Semiconductor memory device and memory system

Also Published As

Publication number Publication date
HRP20170912T1 (hr) 2017-09-22
US9088445B2 (en) 2015-07-21
KR20150126895A (ko) 2015-11-13
US20150194959A1 (en) 2015-07-09
JP2016514316A (ja) 2016-05-19
US20140253173A1 (en) 2014-09-11
EP2965217B1 (en) 2017-04-19
CN105190584A (zh) 2015-12-23
CN105190584B (zh) 2018-10-30
SMT201700382T1 (it) 2017-09-07
KR101742763B1 (ko) 2017-06-01
US9246716B2 (en) 2016-01-26
WO2014138477A1 (en) 2014-09-12
RS56030B1 (sr) 2017-09-29
EP2965217A1 (en) 2016-01-13

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