CN105190584B - 用于基于总线速度选择性地终接双向总线上的信号的方法和装置 - Google Patents
用于基于总线速度选择性地终接双向总线上的信号的方法和装置 Download PDFInfo
- Publication number
- CN105190584B CN105190584B CN201480012111.2A CN201480012111A CN105190584B CN 105190584 B CN105190584 B CN 105190584B CN 201480012111 A CN201480012111 A CN 201480012111A CN 105190584 B CN105190584 B CN 105190584B
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- CN
- China
- Prior art keywords
- equipment
- signal
- logic
- data bus
- bdb
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Sources (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Memory System (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/787,926 US9088445B2 (en) | 2013-03-07 | 2013-03-07 | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
| US13/787,926 | 2013-03-07 | ||
| PCT/US2014/021401 WO2014138477A1 (en) | 2013-03-07 | 2014-03-06 | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105190584A CN105190584A (zh) | 2015-12-23 |
| CN105190584B true CN105190584B (zh) | 2018-10-30 |
Family
ID=50442620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480012111.2A Active CN105190584B (zh) | 2013-03-07 | 2014-03-06 | 用于基于总线速度选择性地终接双向总线上的信号的方法和装置 |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US9088445B2 (enExample) |
| EP (1) | EP2965217B1 (enExample) |
| JP (1) | JP6158960B2 (enExample) |
| KR (1) | KR101742763B1 (enExample) |
| CN (1) | CN105190584B (enExample) |
| HR (1) | HRP20170912T1 (enExample) |
| RS (1) | RS56030B1 (enExample) |
| SM (1) | SMT201700382T1 (enExample) |
| WO (1) | WO2014138477A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9088445B2 (en) * | 2013-03-07 | 2015-07-21 | Qualcomm Incorporated | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
| US9542305B2 (en) * | 2015-01-16 | 2017-01-10 | Harman International Industries, Inc. | Impedance matching for high speed signaling in memory system |
| TWI705666B (zh) * | 2015-06-15 | 2020-09-21 | 日商新力股份有限公司 | 傳送裝置、接收裝置、通信系統 |
| US9910482B2 (en) * | 2015-09-24 | 2018-03-06 | Qualcomm Incorporated | Memory interface with adjustable voltage and termination and methods of use |
| KR102529187B1 (ko) * | 2016-03-31 | 2023-05-04 | 삼성전자주식회사 | 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템 |
| US9825730B1 (en) * | 2016-09-26 | 2017-11-21 | Dell Products, Lp | System and method for optimizing link performance with lanes operating at different speeds |
| WO2022064548A1 (ja) | 2020-09-23 | 2022-03-31 | キオクシア株式会社 | 半導体記憶装置及びメモリシステム |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1385792A (zh) * | 2001-05-14 | 2002-12-18 | 精工爱普生株式会社 | 发送电路、数据传输控制装置及电子机器 |
| US6721212B2 (en) * | 2002-01-09 | 2004-04-13 | Mega Chips Corporation | Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces |
| CN1961560A (zh) * | 2004-03-24 | 2007-05-09 | 高通股份有限公司 | 高数据速率接口装置和方法 |
| US20080112233A1 (en) * | 2006-11-15 | 2008-05-15 | Samsung Electronics Co., Ltd. | On-die termination circuit for semiconductor memory devices |
| US20100142297A1 (en) * | 2008-12-09 | 2010-06-10 | Dong Uk Lee | Data driver |
| CN102194515A (zh) * | 2010-02-23 | 2011-09-21 | 三星电子株式会社 | 片上终结电路、存储器件和模块及操练片上终结器方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5467455A (en) | 1993-11-03 | 1995-11-14 | Motorola, Inc. | Data processing system and method for performing dynamic bus termination |
| JPH1020974A (ja) * | 1996-07-03 | 1998-01-23 | Fujitsu Ltd | バス構造及び入出力バッファ |
| US6557066B1 (en) * | 1999-05-25 | 2003-04-29 | Lsi Logic Corporation | Method and apparatus for data dependent, dual level output driver |
| US6894691B2 (en) | 2002-05-01 | 2005-05-17 | Dell Products L.P. | Dynamic switching of parallel termination for power management with DDR memory |
| US7173450B2 (en) * | 2004-06-01 | 2007-02-06 | Hewlett-Packard Development Company, L.P. | Bus controller |
| KR100670702B1 (ko) | 2004-10-30 | 2007-01-17 | 주식회사 하이닉스반도체 | 온다이 터미네이션 회로를 구비한 반도체 메모리 장치 |
| KR100801033B1 (ko) * | 2005-11-03 | 2008-02-04 | 삼성전자주식회사 | 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법 |
| JP4615461B2 (ja) * | 2006-03-10 | 2011-01-19 | 京セラミタ株式会社 | メモリコントローラ |
| US7864183B1 (en) | 2007-03-08 | 2011-01-04 | Nvidia Corporation | Dynamic switching of memory termination characteristics in a graphics system |
| US7746098B2 (en) | 2008-03-10 | 2010-06-29 | Qimonda North America Corp. | Termination switching based on data rate |
| KR101039862B1 (ko) * | 2008-11-11 | 2011-06-13 | 주식회사 하이닉스반도체 | 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법 |
| KR100980425B1 (ko) | 2008-12-30 | 2010-09-07 | 주식회사 하이닉스반도체 | 글로벌 입출력 라인 터미네이션 제어 회로 |
| US8274308B2 (en) | 2010-06-28 | 2012-09-25 | Intel Corporation | Method and apparatus for dynamic memory termination |
| US9088445B2 (en) * | 2013-03-07 | 2015-07-21 | Qualcomm Incorporated | Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed |
-
2013
- 2013-03-07 US US13/787,926 patent/US9088445B2/en active Active
-
2014
- 2014-03-06 HR HRP20170912TT patent/HRP20170912T1/hr unknown
- 2014-03-06 EP EP14716075.8A patent/EP2965217B1/en active Active
- 2014-03-06 WO PCT/US2014/021401 patent/WO2014138477A1/en not_active Ceased
- 2014-03-06 JP JP2015561679A patent/JP6158960B2/ja not_active Expired - Fee Related
- 2014-03-06 KR KR1020157027341A patent/KR101742763B1/ko not_active Expired - Fee Related
- 2014-03-06 RS RS20170544A patent/RS56030B1/sr unknown
- 2014-03-06 CN CN201480012111.2A patent/CN105190584B/zh active Active
- 2014-03-06 SM SM20170382T patent/SMT201700382T1/it unknown
-
2015
- 2015-03-19 US US14/663,303 patent/US9246716B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1385792A (zh) * | 2001-05-14 | 2002-12-18 | 精工爱普生株式会社 | 发送电路、数据传输控制装置及电子机器 |
| US6721212B2 (en) * | 2002-01-09 | 2004-04-13 | Mega Chips Corporation | Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces |
| CN1961560A (zh) * | 2004-03-24 | 2007-05-09 | 高通股份有限公司 | 高数据速率接口装置和方法 |
| US20080112233A1 (en) * | 2006-11-15 | 2008-05-15 | Samsung Electronics Co., Ltd. | On-die termination circuit for semiconductor memory devices |
| US20100142297A1 (en) * | 2008-12-09 | 2010-06-10 | Dong Uk Lee | Data driver |
| CN102194515A (zh) * | 2010-02-23 | 2011-09-21 | 三星电子株式会社 | 片上终结电路、存储器件和模块及操练片上终结器方法 |
Non-Patent Citations (1)
| Title |
|---|
| 高速总线的数据接口设计;陈喆;《中国优秀硕士学位论文全文数据库信息科技辑》;20090815;第I140-244页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| HRP20170912T1 (hr) | 2017-09-22 |
| US9088445B2 (en) | 2015-07-21 |
| KR20150126895A (ko) | 2015-11-13 |
| US20150194959A1 (en) | 2015-07-09 |
| JP2016514316A (ja) | 2016-05-19 |
| US20140253173A1 (en) | 2014-09-11 |
| EP2965217B1 (en) | 2017-04-19 |
| CN105190584A (zh) | 2015-12-23 |
| JP6158960B2 (ja) | 2017-07-05 |
| SMT201700382T1 (it) | 2017-09-07 |
| KR101742763B1 (ko) | 2017-06-01 |
| US9246716B2 (en) | 2016-01-26 |
| WO2014138477A1 (en) | 2014-09-12 |
| RS56030B1 (sr) | 2017-09-29 |
| EP2965217A1 (en) | 2016-01-13 |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |