SMT201700382T1 - Metodo ed apparato per la terminazione selettiva di segnali su un bus bidirezionale in base alla velocità del bus - Google Patents

Metodo ed apparato per la terminazione selettiva di segnali su un bus bidirezionale in base alla velocità del bus

Info

Publication number
SMT201700382T1
SMT201700382T1 SM20170382T SMT201700382T SMT201700382T1 SM T201700382 T1 SMT201700382 T1 SM T201700382T1 SM 20170382 T SM20170382 T SM 20170382T SM T201700382 T SMT201700382 T SM T201700382T SM T201700382 T1 SMT201700382 T1 SM T201700382T1
Authority
SM
San Marino
Prior art keywords
bus
selectively terminating
terminating signals
speed
bidirectional
Prior art date
Application number
SM20170382T
Other languages
English (en)
Italian (it)
Inventor
Dexter T Chun
Sumeet S Sethi
John D Eaton
Vinodh R Cuppu
Vikram Arora
Vaishnav Srinivas
Muhammad A Muneer
Isaac D Berk
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SMT201700382T1 publication Critical patent/SMT201700382T1/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Memory System (AREA)
SM20170382T 2013-03-07 2014-03-06 Metodo ed apparato per la terminazione selettiva di segnali su un bus bidirezionale in base alla velocità del bus SMT201700382T1 (it)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/787,926 US9088445B2 (en) 2013-03-07 2013-03-07 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
PCT/US2014/021401 WO2014138477A1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
EP14716075.8A EP2965217B1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Publications (1)

Publication Number Publication Date
SMT201700382T1 true SMT201700382T1 (it) 2017-09-07

Family

ID=50442620

Family Applications (1)

Application Number Title Priority Date Filing Date
SM20170382T SMT201700382T1 (it) 2013-03-07 2014-03-06 Metodo ed apparato per la terminazione selettiva di segnali su un bus bidirezionale in base alla velocità del bus

Country Status (9)

Country Link
US (2) US9088445B2 (enExample)
EP (1) EP2965217B1 (enExample)
JP (1) JP6158960B2 (enExample)
KR (1) KR101742763B1 (enExample)
CN (1) CN105190584B (enExample)
HR (1) HRP20170912T1 (enExample)
RS (1) RS56030B1 (enExample)
SM (1) SMT201700382T1 (enExample)
WO (1) WO2014138477A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US9542305B2 (en) * 2015-01-16 2017-01-10 Harman International Industries, Inc. Impedance matching for high speed signaling in memory system
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
KR102529187B1 (ko) * 2016-03-31 2023-05-04 삼성전자주식회사 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
US9825730B1 (en) * 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds
WO2022064548A1 (ja) 2020-09-23 2022-03-31 キオクシア株式会社 半導体記憶装置及びメモリシステム

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH1020974A (ja) * 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
US6557066B1 (en) * 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
JP3651410B2 (ja) * 2001-05-14 2005-05-25 セイコーエプソン株式会社 送信回路、データ転送制御装置及び電子機器
JP3756818B2 (ja) * 2002-01-09 2006-03-15 株式会社メガチップス メモリ制御回路および制御システム
US6894691B2 (en) 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
AU2005227500B2 (en) * 2004-03-24 2008-12-04 Qualcomm Incorporated High data rate interface apparatus and method
US7173450B2 (en) * 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller
KR100670702B1 (ko) 2004-10-30 2007-01-17 주식회사 하이닉스반도체 온다이 터미네이션 회로를 구비한 반도체 메모리 장치
KR100801033B1 (ko) * 2005-11-03 2008-02-04 삼성전자주식회사 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법
JP4615461B2 (ja) * 2006-03-10 2011-01-19 京セラミタ株式会社 メモリコントローラ
KR100790821B1 (ko) 2006-11-15 2008-01-03 삼성전자주식회사 반도체 메모리 장치에서의 온다이 터미네이션 회로
US7864183B1 (en) 2007-03-08 2011-01-04 Nvidia Corporation Dynamic switching of memory termination characteristics in a graphics system
US7746098B2 (en) 2008-03-10 2010-06-29 Qimonda North America Corp. Termination switching based on data rate
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
KR100980417B1 (ko) * 2008-12-09 2010-09-07 주식회사 하이닉스반도체 데이터 드라이버
KR100980425B1 (ko) 2008-12-30 2010-09-07 주식회사 하이닉스반도체 글로벌 입출력 라인 터미네이션 제어 회로
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
US8274308B2 (en) 2010-06-28 2012-09-25 Intel Corporation Method and apparatus for dynamic memory termination
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Also Published As

Publication number Publication date
HRP20170912T1 (hr) 2017-09-22
US9088445B2 (en) 2015-07-21
KR20150126895A (ko) 2015-11-13
US20150194959A1 (en) 2015-07-09
JP2016514316A (ja) 2016-05-19
US20140253173A1 (en) 2014-09-11
EP2965217B1 (en) 2017-04-19
CN105190584A (zh) 2015-12-23
CN105190584B (zh) 2018-10-30
JP6158960B2 (ja) 2017-07-05
KR101742763B1 (ko) 2017-06-01
US9246716B2 (en) 2016-01-26
WO2014138477A1 (en) 2014-09-12
RS56030B1 (sr) 2017-09-29
EP2965217A1 (en) 2016-01-13

Similar Documents

Publication Publication Date Title
GB2499657B (en) Vehicle speed control apparatus and method
GB2511841B (en) Vehicle speed control system and method
GB2518743B (en) Vehicle speed control system and method
GB2516934B (en) Vehicle speed control system and method
GB2511867B (en) Vehicle speed control system and method
EP2991361A4 (en) METHOD, DEVICE AND SYSTEM FOR ENHANCING CHAIN CHANGE SPEED
GB201609571D0 (en) System and method for conducting a multi-channel order
EP2955870A4 (en) Method for transreceiving signals and apparatus for same
EP2941066A4 (en) METHOD AND APPARATUS FOR TRANSMITTING A COMMON SIGNAL
EP3048845A4 (en) SYSTEM AND METHOD FOR DATA TRANSMISSION
PL3063531T3 (pl) Sposób i urządzenie do wykrywania materii
GB2513650B (en) Method and system for cooling a device
GB2546920B (en) Vehicle speed control system and method
HUE051917T2 (hu) Eljárás és eszköz két alrendszer együttes szimulációjához
SMT201700382T1 (it) Metodo ed apparato per la terminazione selettiva di segnali su un bus bidirezionale in base alla velocità del bus
GB2514873B (en) Vehicle speed control system and method
HUE041766T2 (hu) Eljárás és eszköz automatikus jelváltásra több beágyazott CPU-t tartalmazó kártyák között
EP3065324A4 (en) METHOD AND DEVICE FOR PROCESSING SIGNAL COLLECTION POINT DATA
ZA201403403B (en) Apparatus and method for determining a vehicle feature
PL2833349T4 (pl) Sposób przedstawiania stanu istotnego z punktu widzenia bezpieczeństwa
GB201307308D0 (en) A method of, and apparatus for, controlling the speed of a vehicle
GB201600547D0 (en) Apparatus and method for processing signals
GB201313260D0 (en) Vehicle speed control system and method
GB201318493D0 (en) Method and apparatus for characterising amorphous mateials
GB2512912B (en) Apparatus and Method for Signal Predistortion