KR101742763B1 - 버스 속도에 기초하여 양방향성 데이터 버스 상에서 신호들을 선택적으로 종결하기 위한 방법 및 장치 - Google Patents

버스 속도에 기초하여 양방향성 데이터 버스 상에서 신호들을 선택적으로 종결하기 위한 방법 및 장치 Download PDF

Info

Publication number
KR101742763B1
KR101742763B1 KR1020157027341A KR20157027341A KR101742763B1 KR 101742763 B1 KR101742763 B1 KR 101742763B1 KR 1020157027341 A KR1020157027341 A KR 1020157027341A KR 20157027341 A KR20157027341 A KR 20157027341A KR 101742763 B1 KR101742763 B1 KR 101742763B1
Authority
KR
South Korea
Prior art keywords
termination
logic
bus
signals
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020157027341A
Other languages
English (en)
Korean (ko)
Other versions
KR20150126895A (ko
Inventor
덱스터 티. 춘
수미트 에스. 세티
존 디. 이튼
비놉흐 알. 쿱푸
비크람 아로라
바이쉬나브 스리니바스
무함마드 에이. 무너
이삭 디. 벅
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150126895A publication Critical patent/KR20150126895A/ko
Application granted granted Critical
Publication of KR101742763B1 publication Critical patent/KR101742763B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0278Arrangements for impedance matching
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4086Bus impedance matching, e.g. termination
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/017545Coupling arrangements; Impedance matching circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005Modifications of input or output impedance
    • Y02B60/1228
    • Y02B60/1235
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Memory System (AREA)
KR1020157027341A 2013-03-07 2014-03-06 버스 속도에 기초하여 양방향성 데이터 버스 상에서 신호들을 선택적으로 종결하기 위한 방법 및 장치 Expired - Fee Related KR101742763B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/787,926 US9088445B2 (en) 2013-03-07 2013-03-07 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US13/787,926 2013-03-07
PCT/US2014/021401 WO2014138477A1 (en) 2013-03-07 2014-03-06 Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Publications (2)

Publication Number Publication Date
KR20150126895A KR20150126895A (ko) 2015-11-13
KR101742763B1 true KR101742763B1 (ko) 2017-06-01

Family

ID=50442620

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157027341A Expired - Fee Related KR101742763B1 (ko) 2013-03-07 2014-03-06 버스 속도에 기초하여 양방향성 데이터 버스 상에서 신호들을 선택적으로 종결하기 위한 방법 및 장치

Country Status (9)

Country Link
US (2) US9088445B2 (enExample)
EP (1) EP2965217B1 (enExample)
JP (1) JP6158960B2 (enExample)
KR (1) KR101742763B1 (enExample)
CN (1) CN105190584B (enExample)
HR (1) HRP20170912T1 (enExample)
RS (1) RS56030B1 (enExample)
SM (1) SMT201700382T1 (enExample)
WO (1) WO2014138477A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US9542305B2 (en) * 2015-01-16 2017-01-10 Harman International Industries, Inc. Impedance matching for high speed signaling in memory system
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
KR102529187B1 (ko) * 2016-03-31 2023-05-04 삼성전자주식회사 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
US9825730B1 (en) * 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds
WO2022064548A1 (ja) 2020-09-23 2022-03-31 キオクシア株式会社 半導体記憶装置及びメモリシステム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060091900A1 (en) 2004-10-30 2006-05-04 Kang Hee-Bok Semiconductor memory device with on die termination circuit
US20080112233A1 (en) 2006-11-15 2008-05-15 Samsung Electronics Co., Ltd. On-die termination circuit for semiconductor memory devices
US20110316580A1 (en) 2010-06-28 2011-12-29 Mccall James A Method and apparatus for dynamic memory termination

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5467455A (en) 1993-11-03 1995-11-14 Motorola, Inc. Data processing system and method for performing dynamic bus termination
JPH1020974A (ja) * 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
US6557066B1 (en) * 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
JP3651410B2 (ja) * 2001-05-14 2005-05-25 セイコーエプソン株式会社 送信回路、データ転送制御装置及び電子機器
JP3756818B2 (ja) * 2002-01-09 2006-03-15 株式会社メガチップス メモリ制御回路および制御システム
US6894691B2 (en) 2002-05-01 2005-05-17 Dell Products L.P. Dynamic switching of parallel termination for power management with DDR memory
AU2005227500B2 (en) * 2004-03-24 2008-12-04 Qualcomm Incorporated High data rate interface apparatus and method
US7173450B2 (en) * 2004-06-01 2007-02-06 Hewlett-Packard Development Company, L.P. Bus controller
KR100801033B1 (ko) * 2005-11-03 2008-02-04 삼성전자주식회사 경계 스캔 회로를 이용하여 온 다이 터미네이션 회로를테스트할 수 있는 반도체 장치, 이를 구비한 테스트시스템, 및 테스트 방법
JP4615461B2 (ja) * 2006-03-10 2011-01-19 京セラミタ株式会社 メモリコントローラ
US7864183B1 (en) 2007-03-08 2011-01-04 Nvidia Corporation Dynamic switching of memory termination characteristics in a graphics system
US7746098B2 (en) 2008-03-10 2010-06-29 Qimonda North America Corp. Termination switching based on data rate
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
KR100980417B1 (ko) * 2008-12-09 2010-09-07 주식회사 하이닉스반도체 데이터 드라이버
KR100980425B1 (ko) 2008-12-30 2010-09-07 주식회사 하이닉스반도체 글로벌 입출력 라인 터미네이션 제어 회로
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060091900A1 (en) 2004-10-30 2006-05-04 Kang Hee-Bok Semiconductor memory device with on die termination circuit
US20080112233A1 (en) 2006-11-15 2008-05-15 Samsung Electronics Co., Ltd. On-die termination circuit for semiconductor memory devices
US20110316580A1 (en) 2010-06-28 2011-12-29 Mccall James A Method and apparatus for dynamic memory termination

Also Published As

Publication number Publication date
HRP20170912T1 (hr) 2017-09-22
US9088445B2 (en) 2015-07-21
KR20150126895A (ko) 2015-11-13
US20150194959A1 (en) 2015-07-09
JP2016514316A (ja) 2016-05-19
US20140253173A1 (en) 2014-09-11
EP2965217B1 (en) 2017-04-19
CN105190584A (zh) 2015-12-23
CN105190584B (zh) 2018-10-30
JP6158960B2 (ja) 2017-07-05
SMT201700382T1 (it) 2017-09-07
US9246716B2 (en) 2016-01-26
WO2014138477A1 (en) 2014-09-12
RS56030B1 (sr) 2017-09-29
EP2965217A1 (en) 2016-01-13

Similar Documents

Publication Publication Date Title
KR101742763B1 (ko) 버스 속도에 기초하여 양방향성 데이터 버스 상에서 신호들을 선택적으로 종결하기 위한 방법 및 장치
US11250901B2 (en) Protocol for memory power-mode control
US6633178B2 (en) Apparatus and method for power efficient line driver
US10541019B2 (en) Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
US9342095B2 (en) Timing calibration for multimode I/O systems
KR101894469B1 (ko) 제어신호생성회로 및 이를 이용한 반도체모듈 및 반도체시스템
KR101317506B1 (ko) 단일 종단 신호 및 차동 신호에 대한 지연을 매칭시키는 수신기 회로, 집적 회로, 시스템 및 방법
CN110622011B (zh) 用于开漏通信系统的中继器
KR101872997B1 (ko) 조정 가능한 전압 및 종단을 갖는 메모리 인터페이스 및 사용 방법들
KR101205324B1 (ko) 직렬 인터페이스 방식을 갖는 시스템의 전력을 제어하는방법
US7864183B1 (en) Dynamic switching of memory termination characteristics in a graphics system
EP2992400B1 (en) Frequency power manager
US20120170671A1 (en) Integrated circuit chip, system including master chip and slave chip, and operation method thereof
JP3615189B2 (ja) 入出力バッファ回路
CN121002491A (zh) 用于多个信号电平的芯片选择发送器

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
A302 Request for accelerated examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20210527

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20210527