JP2011061351A5 - - Google Patents

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Publication number
JP2011061351A5
JP2011061351A5 JP2009206881A JP2009206881A JP2011061351A5 JP 2011061351 A5 JP2011061351 A5 JP 2011061351A5 JP 2009206881 A JP2009206881 A JP 2009206881A JP 2009206881 A JP2009206881 A JP 2009206881A JP 2011061351 A5 JP2011061351 A5 JP 2011061351A5
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JP
Japan
Prior art keywords
data
switch
circuit
reception
receiving
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JP2009206881A
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English (en)
Japanese (ja)
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JP2011061351A (ja
JP5346259B2 (ja
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Priority claimed from JP2009206881A external-priority patent/JP5346259B2/ja
Priority to JP2009206881A priority Critical patent/JP5346259B2/ja
Priority to US12/876,747 priority patent/US8102186B2/en
Priority to CN201410260671.1A priority patent/CN104113321B/zh
Priority to CN201010279144.7A priority patent/CN102012875B/zh
Publication of JP2011061351A publication Critical patent/JP2011061351A/ja
Priority to US13/271,819 priority patent/US8558572B2/en
Publication of JP2011061351A5 publication Critical patent/JP2011061351A5/ja
Priority to US14/031,462 priority patent/US8952719B2/en
Publication of JP5346259B2 publication Critical patent/JP5346259B2/ja
Application granted granted Critical
Priority to US14/579,364 priority patent/US9286958B2/en
Priority to US15/016,594 priority patent/US9767884B2/en
Priority to US15/684,461 priority patent/US10134462B2/en
Priority to US16/170,209 priority patent/US10490254B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009206881A 2009-09-08 2009-09-08 半導体集積回路 Active JP5346259B2 (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP2009206881A JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路
US12/876,747 US8102186B2 (en) 2009-09-08 2010-09-07 Semiconductor integrated circuit with first and second transmitter-receivers
CN201410260671.1A CN104113321B (zh) 2009-09-08 2010-09-08 半导体集成电路
CN201010279144.7A CN102012875B (zh) 2009-09-08 2010-09-08 半导体集成电路
US13/271,819 US8558572B2 (en) 2009-09-08 2011-10-12 Memory with termination circuit
US14/031,462 US8952719B2 (en) 2009-09-08 2013-09-19 Memory with termination circuit
US14/579,364 US9286958B2 (en) 2009-09-08 2014-12-22 Memory with termination circuit
US15/016,594 US9767884B2 (en) 2009-09-08 2016-02-05 Memory with termination circuit
US15/684,461 US10134462B2 (en) 2009-09-08 2017-08-23 Memory with termination circuit
US16/170,209 US10490254B2 (en) 2009-09-08 2018-10-25 Semiconductor integrated circuit system with termination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009206881A JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013169075A Division JP5591387B2 (ja) 2013-08-16 2013-08-16 記憶装置

Publications (3)

Publication Number Publication Date
JP2011061351A JP2011061351A (ja) 2011-03-24
JP2011061351A5 true JP2011061351A5 (enExample) 2012-04-05
JP5346259B2 JP5346259B2 (ja) 2013-11-20

Family

ID=43647258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009206881A Active JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Country Status (3)

Country Link
US (7) US8102186B2 (enExample)
JP (1) JP5346259B2 (enExample)
CN (2) CN104113321B (enExample)

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KR102646905B1 (ko) * 2016-07-21 2024-03-12 삼성전자주식회사 온 다이 터미네이션 회로, 이를 구비하는 메모리 장치 및 메모리 시스템
US10128841B2 (en) * 2016-09-19 2018-11-13 Mediatek Inc. Termination circuit, receiver and associated terminating method capable of suppressing crosstalk
KR102656219B1 (ko) * 2016-11-07 2024-04-11 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템, 및 그것의 슬루 레이트 조정 방법
KR102717627B1 (ko) * 2016-12-26 2024-10-16 에스케이하이닉스 주식회사 동적 터미네이션 회로, 이를 포함하는 반도체 장치 및 시스템
US10424356B2 (en) 2017-11-22 2019-09-24 Micron Technology, Inc. Methods for on-die memory termination and memory devices and systems employing the same
JP2020102286A (ja) * 2018-12-21 2020-07-02 キオクシア株式会社 半導体記憶装置
KR102767988B1 (ko) * 2020-05-19 2025-02-14 에스케이하이닉스 주식회사 전자시스템 및 반도체시스템

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