JP5346259B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP5346259B2
JP5346259B2 JP2009206881A JP2009206881A JP5346259B2 JP 5346259 B2 JP5346259 B2 JP 5346259B2 JP 2009206881 A JP2009206881 A JP 2009206881A JP 2009206881 A JP2009206881 A JP 2009206881A JP 5346259 B2 JP5346259 B2 JP 5346259B2
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Japan
Prior art keywords
data
circuit
transmission
reception
switch
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Active
Application number
JP2009206881A
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English (en)
Japanese (ja)
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JP2011061351A5 (enExample
JP2011061351A (ja
Inventor
雅泰 光明
洋一 飯塚
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Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009206881A priority Critical patent/JP5346259B2/ja
Priority to US12/876,747 priority patent/US8102186B2/en
Priority to CN201010279144.7A priority patent/CN102012875B/zh
Priority to CN201410260671.1A priority patent/CN104113321B/zh
Publication of JP2011061351A publication Critical patent/JP2011061351A/ja
Priority to US13/271,819 priority patent/US8558572B2/en
Publication of JP2011061351A5 publication Critical patent/JP2011061351A5/ja
Priority to US14/031,462 priority patent/US8952719B2/en
Application granted granted Critical
Publication of JP5346259B2 publication Critical patent/JP5346259B2/ja
Priority to US14/579,364 priority patent/US9286958B2/en
Priority to US15/016,594 priority patent/US9767884B2/en
Priority to US15/684,461 priority patent/US10134462B2/en
Priority to US16/170,209 priority patent/US10490254B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
JP2009206881A 2009-09-08 2009-09-08 半導体集積回路 Active JP5346259B2 (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP2009206881A JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路
US12/876,747 US8102186B2 (en) 2009-09-08 2010-09-07 Semiconductor integrated circuit with first and second transmitter-receivers
CN201410260671.1A CN104113321B (zh) 2009-09-08 2010-09-08 半导体集成电路
CN201010279144.7A CN102012875B (zh) 2009-09-08 2010-09-08 半导体集成电路
US13/271,819 US8558572B2 (en) 2009-09-08 2011-10-12 Memory with termination circuit
US14/031,462 US8952719B2 (en) 2009-09-08 2013-09-19 Memory with termination circuit
US14/579,364 US9286958B2 (en) 2009-09-08 2014-12-22 Memory with termination circuit
US15/016,594 US9767884B2 (en) 2009-09-08 2016-02-05 Memory with termination circuit
US15/684,461 US10134462B2 (en) 2009-09-08 2017-08-23 Memory with termination circuit
US16/170,209 US10490254B2 (en) 2009-09-08 2018-10-25 Semiconductor integrated circuit system with termination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009206881A JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013169075A Division JP5591387B2 (ja) 2013-08-16 2013-08-16 記憶装置

Publications (3)

Publication Number Publication Date
JP2011061351A JP2011061351A (ja) 2011-03-24
JP2011061351A5 JP2011061351A5 (enExample) 2012-04-05
JP5346259B2 true JP5346259B2 (ja) 2013-11-20

Family

ID=43647258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009206881A Active JP5346259B2 (ja) 2009-09-08 2009-09-08 半導体集積回路

Country Status (3)

Country Link
US (7) US8102186B2 (enExample)
JP (1) JP5346259B2 (enExample)
CN (2) CN102012875B (enExample)

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US7486104B2 (en) 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
JP5390310B2 (ja) 2009-09-08 2014-01-15 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5346259B2 (ja) 2009-09-08 2013-11-20 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5363252B2 (ja) 2009-09-09 2013-12-11 ルネサスエレクトロニクス株式会社 半導体集積回路
WO2011159465A2 (en) 2010-06-17 2011-12-22 Rambus Inc. Balanced on-die termination
CN103066987A (zh) * 2011-10-24 2013-04-24 三星电子株式会社 输出驱动器、集成电路及系统
KR20130045144A (ko) * 2011-10-24 2013-05-03 삼성전자주식회사 출력 드라이버와 이를 포함하는 장치들, 및 접지 터미네이션
FR3001310B1 (fr) * 2013-01-21 2015-02-27 Commissariat Energie Atomique Interface de reseau sur puce dotee d'un systeme adaptatif de declenchement d'envoi de donnees
CN104517625B (zh) * 2013-09-29 2017-07-28 瑞昱半导体股份有限公司 电子装置与用于电子装置的控制方法
JP6402579B2 (ja) * 2014-10-17 2018-10-10 株式会社ソシオネクスト 送受信回路及び制御方法
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JP6509711B2 (ja) * 2015-10-29 2019-05-08 東芝メモリ株式会社 不揮発性半導体記憶装置及びメモリシステム
KR102529187B1 (ko) * 2016-03-31 2023-05-04 삼성전자주식회사 복수의 통신 규격들을 지원하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
KR102646905B1 (ko) * 2016-07-21 2024-03-12 삼성전자주식회사 온 다이 터미네이션 회로, 이를 구비하는 메모리 장치 및 메모리 시스템
US10128841B2 (en) * 2016-09-19 2018-11-13 Mediatek Inc. Termination circuit, receiver and associated terminating method capable of suppressing crosstalk
KR102656219B1 (ko) * 2016-11-07 2024-04-11 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 시스템, 및 그것의 슬루 레이트 조정 방법
KR102717627B1 (ko) * 2016-12-26 2024-10-16 에스케이하이닉스 주식회사 동적 터미네이션 회로, 이를 포함하는 반도체 장치 및 시스템
US10424356B2 (en) 2017-11-22 2019-09-24 Micron Technology, Inc. Methods for on-die memory termination and memory devices and systems employing the same
JP2020102286A (ja) * 2018-12-21 2020-07-02 キオクシア株式会社 半導体記憶装置
KR102767988B1 (ko) * 2020-05-19 2025-02-14 에스케이하이닉스 주식회사 전자시스템 및 반도체시스템

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Also Published As

Publication number Publication date
US20170352401A1 (en) 2017-12-07
US8102186B2 (en) 2012-01-24
US20110057720A1 (en) 2011-03-10
CN102012875A (zh) 2011-04-13
US20120026812A1 (en) 2012-02-02
CN102012875B (zh) 2014-07-09
US8558572B2 (en) 2013-10-15
US20150109869A1 (en) 2015-04-23
CN104113321B (zh) 2017-08-29
US9767884B2 (en) 2017-09-19
US10134462B2 (en) 2018-11-20
US20160155489A1 (en) 2016-06-02
US8952719B2 (en) 2015-02-10
US20140016401A1 (en) 2014-01-16
US10490254B2 (en) 2019-11-26
US20190066756A1 (en) 2019-02-28
JP2011061351A (ja) 2011-03-24
CN104113321A (zh) 2014-10-22
US9286958B2 (en) 2016-03-15

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