JP2016189456A - 半導体素子の製造装置及びこれを用いた半導体素子の製造方法 - Google Patents
半導体素子の製造装置及びこれを用いた半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 78
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 106
- 239000001257 hydrogen Substances 0.000 claims abstract description 105
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 76
- 238000006356 dehydrogenation reaction Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 150000002431 hydrogen Chemical class 0.000 claims abstract description 14
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 119
- 230000008569 process Effects 0.000 claims description 99
- 239000010409 thin film Substances 0.000 claims description 46
- 230000001678 irradiating effect Effects 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 22
- 238000012545 processing Methods 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 21
- 230000008016 vaporization Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 18
- -1 hydrogen ions Chemical class 0.000 description 15
- 230000008859 change Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
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Abstract
【解決手段】本発明は、基板の上に水素を含有する被処理層が形成された被処理物に2段階に亘って光が照射されるように熱源ユニットを制御しながら脱水素化を行うことにより、水素による半導体素子の電気的な特性の低下が抑制及び防止される。すなわち、1段階目に照射される紫外線(UV)は被処理層内のSi−H結合を切断する化学的な反応を誘導し、2段階目に照射される赤外線(IR)系の光はSi−H結合から分離された水素を気化する熱伝反応を誘導する。このように、被処理層内において水素と他のイオンとの間の結合を切断する化学的な反応及び水素を気化する熱的反応が共に行われることにより、熱的反応のみを用いて被処理層から水素を気化するときの温度よりも低い温度で容易に被処理層内の水素を除去することができる。
【選択図】図4
Description
S1:第1の被処理物
S2:第2の被処理物
S3:第3の被処理物
1:半導体素子の製造装置
100:チャンバ
110:上部チャンバ
130:下部チャンバ
200:ステージ
300:熱源ユニット
310:第1のランプ
330:第2のランプ
400:制御部
A:1次光源
B:2次光源
Claims (19)
- 被処理物が処理される空間を提供するチャンバと、
前記チャンバ内に配置され、上面に前記被処理物を載置するステージと、
前記ステージの上方に離隔配置され、前記被処理物に2段階に亘って光を照射する熱源ユニットと、
前記熱源ユニットに接続されて2段階に亘って光が照射されるように前記熱源ユニットを制御する制御部と、
を備える半導体素子の製造装置。 - 前記熱源ユニットは、
前記被処理物に紫外線を照射する第1のランプと、
紫外線が照射された被処理物に赤外線を照射する第2のランプと、
を備える請求項1に記載の半導体素子の製造装置。 - 前記第1のランプは、前記第2のランプを囲繞するように配置される請求項2に記載の半導体素子の製造装置。
- 前記被処理物の照射面の全体の面積を基準として、前記第1のランプの照射面積は、前記第2のランプの照射面積よりも大きい請求項3に記載の半導体素子の製造装置。
- 前記制御部は、前記第1のランプが作動した後に前記第2のランプが作動するように前記熱源ユニットを制御する請求項2乃至請求項4のうちのいずれか一項に記載の半導体素子の製造装置。
- 前記制御部は、
前記第1のランプの作動が止まると同時に前記第2のランプを作動する請求項5に記載の半導体素子の製造装置。 - 前記制御部は、
前記第1のランプの作動が止まった後に時間差をおいて前記第2のランプを作動する請求項5に記載の半導体素子の製造装置。 - 前記制御部は、
前記第1のランプの作動タイミングと前記第2のランプの作動タイミングとを重ならせる請求項5に記載の半導体素子の製造装置。 - 前記被処理物は、基板と、前記基板の上に水素を含有して形成される被処理層と、を有し、
前記被処理層は、前記基板の上に水素(H)を含むソースを用いて化学気相蒸着CVD方法により形成した薄膜である請求項1に記載の半導体素子の製造装置。 - ソース及びドレイン電極を有する半導体素子を製造する方法であって、
基板の上に水素を含有する被処理層を形成する過程と、
前記被処理層に2段階に亘って光を照射して脱水素化を行う過程と、
を含む半導体素子の製造方法。 - 前記脱水素化を行う過程は、
前記被処理層内のSi−Hの化学的な結合を切断する1次光照射過程と、
前記1次光照射過程の後に、分離された水素(H)を気化する2次光照射過程と、
を含む請求項10に記載の半導体素子の製造方法。 - 前記脱水素化を行う過程は、350℃〜400℃において行われる請求項10に記載の半導体素子の製造方法。
- 前記脱水素化を行う過程は、
前記基板の上にゲート電極を形成し、前記ゲート電極の上に前記被処理層としてゲート絶縁膜を形成する過程の後に行われる請求項10乃至請求項12のうちのいずれか一項に記載の半導体素子の製造方法。 - 前記脱水素化を行う過程は、
前記基板の上に前記ソース及びドレイン電極を形成し、前記ソース及びドレイン電極の上にアクティブパターンを形成し、前記アクティブパターンの上に前記被処理層としてゲート絶縁膜を形成する過程の後に行われる請求項10乃至請求項12のうちのいずれか一項に記載の半導体素子の製造方法。 - 前記脱水素化を行う過程は、
前記基板の上に前記被処理層として非晶質シリコンを形成する過程の後に行われる請求項10乃至請求項12のうちのいずれか一項に記載の半導体素子の製造方法。 - 前記被処理層内のSi−Hの化学的な結合を切断する1次光は紫外線であり、前記分離された水素(H)を気化する2次光は赤外線系である請求項11に記載の半導体素子の製造方法。
- 前記1次光照射過程及び前記2次光照射過程は、同一の空間において行われる請求項11に記載の半導体素子の製造方法。
- 前記1次光照射過程及び前記2次光照射過程は、互いに異なる空間において行われる請求項11に記載の半導体素子の製造方法。
- 前記被処理層は、前記基板の上に水素(H)を含むソースを用いて化学気相蒸着CVD方法により形成した薄膜である請求項10に記載の半導体素子の製造方法。
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