JP2016163004A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2016163004A JP2016163004A JP2015043410A JP2015043410A JP2016163004A JP 2016163004 A JP2016163004 A JP 2016163004A JP 2015043410 A JP2015043410 A JP 2015043410A JP 2015043410 A JP2015043410 A JP 2015043410A JP 2016163004 A JP2016163004 A JP 2016163004A
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Abstract
Description
第1半導体領域は、第1方向に延びている。第1半導体領域は、第1方向と交差する第2方向において複数設けられている。
第2半導体領域は、第1方向に延びている。第1半導体領域と第2半導体領域は、第2方向において交互に設けられている。少なくとも1つの第2半導体領域は、空隙を有する。空隙を形成する面のうち少なくとも1つの面の面方位は、(100)である。
第3半導体領域は、第2半導体領域の上に設けられている。
第4半導体領域は、第3半導体領域の上に選択的に設けられている。
ゲート絶縁層は、第3半導体領域とゲート電極との間に設けられている。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
また、本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
以下の説明において、n+、n−及びp+、p、p−の表記は、各導電形における不純物濃度の相対的な高低を表す。すなわち、n+はn−よりもn形の不純物濃度が相対的に高いことを示す。また、p+はpよりもp形の不純物濃度が相対的に高く、p−はpよりもp形の不純物濃度が相対的に低いことを示す。
以下で説明する各実施形態について、各半導体領域のp形とn形を反転させて各実施形態を実施してもよい。
第1実施形態に係る半導体装置100について、図1〜図3を用いて説明する。
図1は、第1実施形態に係る半導体装置100の一部を表す斜視断面図である。
図2は、図1の一部を拡大した断面図である。
図3は、第1実施形態に係る半導体装置100の一部を表す平面図である。
第1実施形態に係る半導体装置100は、n+形ドレイン領域15と、n−形半導体層10と、p−形半導体領域12(第2導電形の第2半導体領域)と、p形ベース領域13(第3半導体領域)と、n+形ソース領域14(第4半導体領域)と、p+形コンタクト領域16と、ゲート電極20と、ゲート絶縁層21と、ドレイン電極30と、ソース電極31と、を有する。n−形半導体層10は、n−形半導体領域11(第1導電形の第1半導体領域)を有する。
p−形半導体領域12は、例えば、図2に表すように、第1部分121と、第2部分122と、を有する。
図3に表すように、空隙25は、Y方向に延びている。第1面S1および第4面S4は、Y方向に沿って延びている。
図4〜図11は、第1実施形態に係る半導体装置100の製造工程を表わす工程断面図である。
本実施形態では、p−形半導体領域12が空隙25を有し、この空隙25を形成する面のうち少なくとも1つの面の面方位は(100)である。このような構成を採用することで、半導体装置を製造する際の歩留まりを向上させることができる。
例えば、開口OP1の側壁の面方位が(110)である場合、Siは、(111)面を現しながら側壁の上に成長していく。この場合、開口OP1の開口端付近の成長速度が、底部付近の成長速度よりも早くなるとともに、開口端が塞がれた後に、空隙の上方に転位が形成されやすい。転位が形成されると、転位が形成された部分をリーク電流が流れる可能性がある。このため、例えば、MOSFETがオフ状態であるにも関わらず、電流が流れてしまうなどの課題が生じうる。この結果、半導体装置の歩留まりが低下してしまう。また、この場合、空隙25を形成する面の面方位は、(100)以外の面方位となる。
従って、空隙25を形成する面のうち、X方向と交差する面、Y方向と交差する面、およびX方向と交差する面の面方位がいずれも(100)である場合、空隙を有する半導体装置を製造する際の歩留まりをより一層向上させることができる。
第2実施形態に係る半導体装置200について、図12および図13を用いて説明する。
図12は、第2実施形態に係る半導体装置200の一部を表す斜視断面図である。
図13は、図12の一部を拡大した断面図である。
図14〜図17は、第2実施形態に係る半導体装置200の製造工程を表わす工程断面図である。
また、各半導体領域における不純物濃度については、例えば、SIMS(二次イオン質量分析法)により測定することが可能である。
Claims (10)
- 第1方向に延び、前記第1方向と交差する第2方向において複数設けられた第1導電形の第1半導体領域と、
前記第1方向に延び、前記第2方向において前記第1半導体領域と交互に設けられ、少なくとも1つが空隙を有し、前記空隙を形成する面のうち少なくとも1つの面の面方位は(100)である、第2導電形の複数の第2半導体領域と、
前記第2半導体領域の上に設けられた第2導電形の第3半導体領域と、
前記第3半導体領域の上に選択的に設けられた第1導電形の第4半導体領域と、
ゲート電極と、
前記第3半導体領域と前記ゲート電極との間に設けられたゲート絶縁層と、
を備えた半導体装置。 - 前記少なくとも1つの前記第2半導体領域は、
前記第1方向に交差する第1面と、
前記第1方向および前記第2方向に対して垂直な第3方向に交差する第2面と、
を有し、
前記第1面の面方位および前記第2面の面方位は、(100)であり、
前記空隙は、前記第1面および前記第2面を含む複数の面により形成された請求項1記載の半導体装置。 - 前記少なくとも1つの前記第2半導体領域は、
第1部分と、
第1部分と第1半導体領域との間に設けられ、第1部分の第2導電形のキャリア濃度よりも高い第2導電形のキャリア濃度を有する第2部分と、
を有し、
前記空隙は、前記第1部分に設けられた請求項1または2に記載の半導体装置。 - 前記空隙は、前記第1方向に延びる請求項1〜3のいずれか1つに記載の半導体装置。
- 前記第3半導体領域の上に選択的に設けられた第2導電形の第5半導体領域をさらに備え、
前記第5半導体領域における第2導電形のキャリア濃度は、前記第3半導体領域における第2導電形のキャリア濃度よりも高く、
前記第5半導体領域の少なくとも一部は、前記第1方向および前記第2方向に対して垂直な第3方向において、前記空隙の少なくとも一部と並んだ請求項1〜4のいずれか1つに記載の半導体装置。 - 第1方向に並べられ、それぞれが前記第1方向と交差する第2方向に延びる複数の突出部を第1導電形の第1半導体層の上部に形成する工程と、
前記第1方向と、前記第1方向および前記第2方向に直交する第3方向と、において、それぞれが前記突出部のそれぞれに重なる複数のマスクを形成する工程と、
前記複数のマスクを用いて前記第1半導体層に開口を形成する工程と、
前記開口の内部に、空隙を有する第2半導体層を形成する工程と、
を備えた半導体装置の製造方法。 - 前記開口の内壁に沿って、第2導電形の第3半導体層を形成する工程をさらに備え、
前記第2半導体層は、前記第3半導体層の上に形成され、
前記第2半導体層における第2導電形のキャリア濃度は、前記第3半導体層における第2導電形のキャリア濃度よりも低い請求項6記載の半導体装置の製造方法。 - 前記第2半導体層を形成した後に前記マスクを除去する工程と、
前記マスクを除去した後に、第1半導体層、前記第2半導体層、および前記第3半導体層を加熱する工程と、
をさらに備えた請求項7記載の半導体装置の製造方法。 - 前記加熱工程によって、前記第1半導体層の上面の前記第3方向における位置と、前記第2半導体層の上面の前記第3方向における位置と、を変化させる請求項8記載の半導体装置の製造方法。
- 前記第1半導体層の一部および前記第2半導体層の一部に第2導電形の第3半導体領域を形成する工程と、
前記第3半導体領域の上に選択的に第1導電形の第4半導体領域を形成する工程と、
前記第3半導体領域と、ゲート絶縁層を介して対向するゲート電極を形成する工程と、
をさらに備えた請求項6〜9のいずれか1つに記載の半導体装置の製造方法。
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KR1020150103669A KR20160108099A (ko) | 2015-03-05 | 2015-07-22 | 반도체 장치 및 반도체 장치의 제조 방법 |
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TW104128919A TW201633408A (zh) | 2015-03-05 | 2015-09-02 | 半導體裝置及半導體裝置之製造方法 |
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WO2019224913A1 (ja) * | 2018-05-22 | 2019-11-28 | サンケン電気株式会社 | 半導体装置 |
US11764059B2 (en) | 2019-10-09 | 2023-09-19 | Kabushiki Kaisha Toshiba | Method for manufacturing substrate, method for manufacturing semiconductor device, substrate, and semiconductor device |
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US11355630B2 (en) * | 2020-09-11 | 2022-06-07 | Wolfspeed, Inc. | Trench bottom shielding methods and approaches for trenched semiconductor device structures |
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