JP2015528608A - デュアルモードピン配列を有するフラッシュメモリコントローラ - Google Patents
デュアルモードピン配列を有するフラッシュメモリコントローラ Download PDFInfo
- Publication number
- JP2015528608A JP2015528608A JP2015531407A JP2015531407A JP2015528608A JP 2015528608 A JP2015528608 A JP 2015528608A JP 2015531407 A JP2015531407 A JP 2015531407A JP 2015531407 A JP2015531407 A JP 2015531407A JP 2015528608 A JP2015528608 A JP 2015528608A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- signal
- interface
- circuit
- memory interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
Description
本願は、2012年9月19日に出願された米国仮特許出願第61/702,846号明細書、2012年10月12日に出願された米国仮特許出願第61/713,008号明細書、及び米国特許出願第13/835,968号明細書の利益を主張するものであり、これらを参照により本明細書に援用する。
Claims (21)
- 回路を含む少なくとも1つのメモリインタフェースポートを有するメモリインタフェースであって、前記回路は、少なくとも、第1のメモリインタフェースプロトコルでの通信に準拠した第1の信号又は前記第1のメモリインタフェースプロトコルとは異なる第2のメモリインタフェースプロトコルでの通信に準拠した第2の信号をバッファリングするように構成される、メモリインタフェースと、
ホスト装置と前記メモリインタフェースとの間で情報を通信するホストインタフェースポートを有するホストインタフェースと、
を備える、デュアルインタフェースメモリコントローラ。 - 印加される電圧レベルに応答して、前記第1の信号の経路又は前記第2の信号の経路をイネーブルするモードセレクタ回路を更に含む、請求項1に記載のデュアルインタフェースメモリコントローラ。
- 前記モードセレクタ回路に電気的に結合されて、前記印加される電圧レベルを受け取るパッドを更に含む、請求項2に記載のデュアルインタフェースメモリコントローラ。
- 前記回路は、前記第1の信号をバッファリングするように構成される第1の信号経路と、前記第2の信号をバッファリングするように構成される第2の信号経路とを含む、請求項2に記載のデュアルインタフェースメモリコントローラ。
- 前記少なくとも1つのメモリインタフェースポートは単一のパッドを含む、請求項4に記載のデュアルインタフェースメモリコントローラ。
- 前記第1の信号経路は、前記第1のメモリインタフェースプロトコルに対応する入力信号を前記単一のパッドから受信するように構成される入力回路を含む、請求項5に記載のデュアルインタフェースメモリコントローラ。
- 入力回路は第1の入力回路であり、前記第2の信号経路は、前記第2のメモリインタフェースプロトコルに対応する別の入力信号を前記単一のパッドから受信するように構成される第2の入力回路を含む、請求項6に記載のデュアルインタフェースメモリコントローラ。
- 前記モードセレクタ回路によって提供される第1の論理状態及び第2の論理状態のうちの一方を有する選択信号に応答して、前記単一のパッドを前記第1の入力回路又は前記第2の入力回路のうちの一方に選択的に結合するセレクタ回路を更に含む、請求項7に記載のデュアルインタフェースメモリコントローラ。
- 前記第2の信号経路は、前記第2のメモリインタフェースプロトコルに対応する出力信号を前記単一のパッドに提供するように構成される出力回路を含む、請求項6に記載のデュアルインタフェースメモリコントローラ。
- 前記回路は、第3の信号をバッファリングするように構成される第3の信号経路を含み、前記第3の信号は、前記第1のメモリインタフェースプロトコルに対応する、請求項8に記載のデュアルインタフェースメモリコントローラ。
- 前記第3の信号経路は、前記メモリインタフェースプロトコルに対応する出力信号を前記単一のパッドに提供するように構成される出力回路を含む、請求項10に記載のデュアルインタフェースメモリコントローラ。
- 前記少なくとも1つのメモリインタフェースポートは、前記第1の論理状態の前記選択信号によってイネーブルされて、前記出力信号で前記単一のパッドを駆動する出力駆動回路を含み、前記セレクタ回路は、前記選択信号が前記第1の論理状態である場合、前記単一のパッドを前記第2の入力回路に結合する、請求項11に記載のデュアルインタフェースメモリコントローラ。
- 前記第1の信号経路は、前記第1のメモリインタフェースプロトコルに対応する出力信号を前記単一のパッドに提供するように構成される出力回路を含む、請求項5に記載のデュアルインタフェースメモリコントローラ。
- 前記出力回路は第1の出力回路であり、前記第2の信号経路は、前記第2のメモリインタフェースプロトコルに対応する別の出力信号を前記単一のパッドに提供するように構成される第2の出力回路を含む、請求項13に記載のデュアルインタフェースメモリコントローラ。
- 前記モードセレクタ回路によって提供される第1の論理状態及び第2の論理状態のうちの一方を有する選択信号に応答して、前記単一のパッドを前記第1の出力回路又は前記第2の出力回路のうちの一方に選択的に結合するセレクタ回路を更に含む、請求項14に記載のデュアルインタフェースメモリコントローラ。
- 前記第1のメモリインタフェースプロトコルは、ONFiメモリインタフェースプロトコルであり、前記第2のメモリインタフェースプロトコルは、HLNANDメモリインタフェースプロトコルである、請求項1に記載のデュアルインタフェースメモリコントローラ。
- 不揮発性メモリシステムであって、
ホスト装置からの要求に応答して、第1のメモリインタフェースプロトコルピン配列及び第2のメモリインタフェースプロトコルピン配列のうちの一方に対応する信号をバッファリングする回路が構成される少なくとも1つの入/出力ポートを有するチャネル制御モジュールを含むメモリコントローラと、
前記少なくとも1つの入/出力ポートを通して前記チャネル制御モジュールと通信する前記第1のメモリインタフェースプロトコルピン配列又は第2のメモリインタフェースプロトコルピン配列のうちのいずれかを有する少なくとも1つのメモリと、
を備える、不揮発性メモリシステム。 - 前記少なくとも1つの入/出力ポートを前記少なくとも1つのメモリ素子に電気的に接続するチャネルを更に含む、請求項17に記載の不揮発性メモリシステム。
- 前記少なくとも1つのメモリは、前記チャネルに並列接続される少なくとも2つのメモリチップを含む、請求項18に記載の不揮発性メモリシステム。
- 前記少なくとも1つのメモリは、前記チャネル制御モジュールとリングトポロジ構成で直列接続される少なくとも2つのメモリチップを含む、請求項18に記載の不揮発性メモリシステム。
- 前記第1のメモリインタフェースプロトコルピン配列は、ONFiメモリインタフェースピン配列に対応し、前記第2のメモリインタフェースプロトコルピン配列は、HLNANDメモリインタフェースピン配列に対応する、請求項17に記載の不揮発性メモリシステム。
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261702846P | 2012-09-19 | 2012-09-19 | |
US61/702,846 | 2012-09-19 | ||
US201261713008P | 2012-10-12 | 2012-10-12 | |
US61/713,008 | 2012-10-12 | ||
US13/835,968 US9471484B2 (en) | 2012-09-19 | 2013-03-15 | Flash memory controller having dual mode pin-out |
US13/835,968 | 2013-03-15 | ||
PCT/CA2013/000782 WO2014043788A1 (en) | 2012-09-19 | 2013-09-18 | Flash memory controller having dual mode pin-out |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015528608A true JP2015528608A (ja) | 2015-09-28 |
JP6386460B2 JP6386460B2 (ja) | 2018-09-05 |
Family
ID=50275695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015531407A Expired - Fee Related JP6386460B2 (ja) | 2012-09-19 | 2013-09-18 | デュアルモードピン配列を有するフラッシュメモリコントローラ |
Country Status (6)
Country | Link |
---|---|
US (1) | US9471484B2 (ja) |
JP (1) | JP6386460B2 (ja) |
KR (1) | KR102113359B1 (ja) |
CN (1) | CN104704563B (ja) |
TW (1) | TWI595488B (ja) |
WO (1) | WO2014043788A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019160307A (ja) * | 2018-03-09 | 2019-09-19 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 適応型インターフェイスストレージ装置 |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8560604B2 (en) | 2009-10-08 | 2013-10-15 | Hola Networks Ltd. | System and method for providing faster and more efficient data communication |
IL210169A0 (en) | 2010-12-22 | 2011-03-31 | Yehuda Binder | System and method for routing-based internet security |
EP2761472B1 (en) | 2011-09-30 | 2020-04-01 | Intel Corporation | Memory channel that supports near memory and far memory access |
US9324389B2 (en) * | 2013-05-29 | 2016-04-26 | Sandisk Technologies Inc. | High performance system topology for NAND memory systems |
US9728526B2 (en) | 2013-05-29 | 2017-08-08 | Sandisk Technologies Llc | Packaging of high performance system topology for NAND memory systems |
US9241044B2 (en) | 2013-08-28 | 2016-01-19 | Hola Networks, Ltd. | System and method for improving internet communication by using intermediate nodes |
US20150161038A1 (en) * | 2013-12-10 | 2015-06-11 | Conversant Intellectual Property Management Inc. | System and Method of Operation for High Capacity Solid-State Drive |
US20150261446A1 (en) * | 2014-03-12 | 2015-09-17 | Futurewei Technologies, Inc. | Ddr4-onfi ssd 1-to-n bus adaptation and expansion controller |
US10691838B2 (en) * | 2014-06-20 | 2020-06-23 | Cypress Semiconductor Corporation | Encryption for XIP and MMIO external memories |
US10121013B2 (en) | 2015-05-07 | 2018-11-06 | Samsung Electronics Co., Ltd. | XOR-based scrambler/descrambler for SSD communication protocols |
US11057446B2 (en) | 2015-05-14 | 2021-07-06 | Bright Data Ltd. | System and method for streaming content from multiple servers |
KR102417182B1 (ko) * | 2015-06-22 | 2022-07-05 | 삼성전자주식회사 | 데이터 저장 장치와 이를 포함하는 데이터 처리 시스템 |
US10423545B2 (en) * | 2015-07-08 | 2019-09-24 | International Business Machines Corporation | Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus |
US10241937B2 (en) | 2015-07-08 | 2019-03-26 | International Business Machines Corporation | Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus |
US10114788B2 (en) | 2015-07-08 | 2018-10-30 | International Business Machines Corporation | Adjusting an optimization parameter to customize a signal eye for a target chip on a shared bus |
KR20170046862A (ko) * | 2015-10-21 | 2017-05-04 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
US10621119B2 (en) * | 2016-03-03 | 2020-04-14 | Samsung Electronics Co., Ltd. | Asynchronous communication protocol compatible with synchronous DDR protocol |
US10310547B2 (en) * | 2016-03-05 | 2019-06-04 | Intel Corporation | Techniques to mirror a command/address or interpret command/address logic at a memory device |
CN105788636A (zh) * | 2016-04-05 | 2016-07-20 | 山东华芯半导体有限公司 | 一种基于并行多通道结构的eMMC控制器 |
US10824348B2 (en) * | 2016-08-02 | 2020-11-03 | Samsung Electronics Co., Ltd. | Method of executing conditional data scrubbing inside a smart storage device |
JP2018032141A (ja) * | 2016-08-23 | 2018-03-01 | 東芝メモリ株式会社 | 半導体装置 |
KR102669694B1 (ko) * | 2016-09-28 | 2024-05-28 | 삼성전자주식회사 | 서로 직렬로 연결된 스토리지 장치들 중 애플리케이션 프로세서에 직접 연결되지 않는 스토리지 장치를 리셋시키는 전자 기기 및 그것의 동작 방법 |
JP2018073438A (ja) * | 2016-10-24 | 2018-05-10 | 東芝メモリ株式会社 | 半導体記憶装置 |
KR20180095765A (ko) * | 2017-02-17 | 2018-08-28 | 삼성전자주식회사 | 스토리지 장치 및 스토리지 장치의 동작 방법 |
TWI690806B (zh) * | 2017-05-22 | 2020-04-11 | 義隆電子股份有限公司 | 串列周邊介面之資料傳送裝置與資料接收裝置 |
JP2019053444A (ja) | 2017-09-13 | 2019-04-04 | 東芝メモリ株式会社 | 半導体集積回路及び半導体装置 |
CN118051268A (zh) * | 2017-09-27 | 2024-05-17 | 北京忆芯科技有限公司 | 电子设备及其启动方法 |
KR102535243B1 (ko) * | 2017-12-18 | 2023-05-23 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
KR20190118428A (ko) * | 2018-04-10 | 2019-10-18 | 에스케이하이닉스 주식회사 | 컨트롤러 및 이를 포함하는 메모리 시스템 |
US10877678B2 (en) | 2018-05-17 | 2020-12-29 | Micron Technology, Inc. | Selection component that is configured based on an architecture associated with memory devices |
KR102605637B1 (ko) | 2018-07-27 | 2023-11-24 | 에스케이하이닉스 주식회사 | 반도체 장치 및 데이터 처리 시스템 |
WO2020076718A1 (en) * | 2018-10-12 | 2020-04-16 | Rambus Inc. | Command buffer chip with dual configurations |
US10901734B2 (en) * | 2019-03-01 | 2021-01-26 | Micron Technology, Inc. | Memory mapping using commands to transfer data and/or perform logic operations |
US10811057B1 (en) | 2019-03-26 | 2020-10-20 | Micron Technology, Inc. | Centralized placement of command and address in memory devices |
US10978117B2 (en) | 2019-03-26 | 2021-04-13 | Micron Technology, Inc. | Centralized placement of command and address swapping in memory devices |
US10811059B1 (en) | 2019-03-27 | 2020-10-20 | Micron Technology, Inc. | Routing for power signals including a redistribution layer |
US11031335B2 (en) | 2019-04-03 | 2021-06-08 | Micron Technology, Inc. | Semiconductor devices including redistribution layers |
CN112069085B (zh) * | 2019-06-10 | 2023-06-02 | 苏州库瀚信息科技有限公司 | 双模式闪存控制器和双模式存储器通信的系统、方法 |
US11416422B2 (en) * | 2019-09-17 | 2022-08-16 | Micron Technology, Inc. | Memory chip having an integrated data mover |
US11417372B2 (en) | 2020-03-06 | 2022-08-16 | Micron Technology, Inc. | Interface protocol configuration for memory |
JP2021149814A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置及び制御方法 |
CN111383154A (zh) * | 2020-04-02 | 2020-07-07 | 广东金宇恒软件科技有限公司 | 一种数据接口及便于管理的公共财政预算管理一体化平台系统 |
CN111883037A (zh) * | 2020-07-28 | 2020-11-03 | 重庆惠科金渝光电科技有限公司 | 时序控制板、驱动装置和显示装置 |
CN111833797A (zh) * | 2020-07-28 | 2020-10-27 | 重庆惠科金渝光电科技有限公司 | 时序控制板、驱动装置和显示装置 |
TWI816046B (zh) * | 2020-08-19 | 2023-09-21 | 創惟科技股份有限公司 | 記憶體儲存裝置的讀寫控制系統及方法 |
CN112912864B (zh) * | 2021-02-03 | 2023-10-31 | 长江存储科技有限责任公司 | 用于对闪存模块直接访问的方法和系统 |
US11567699B2 (en) * | 2021-02-04 | 2023-01-31 | Silicon Motion, Inc. | Memory controller having a plurality of control modules and associated server |
JP2023035640A (ja) | 2021-09-01 | 2023-03-13 | キオクシア株式会社 | メモリシステム |
US11841764B2 (en) * | 2021-12-17 | 2023-12-12 | Infineon Technologies LLC | Circuit and method for reading ECC from memory |
EP4276639A1 (en) * | 2022-05-09 | 2023-11-15 | Samsung Electronics Co., Ltd. | Computing system including memory device and storage device and operating method thereof |
US20240095199A1 (en) * | 2022-09-15 | 2024-03-21 | Micron Technology, Inc. | Multi-interface memory |
CN115904254B (zh) * | 2023-01-09 | 2023-06-02 | 苏州浪潮智能科技有限公司 | 一种硬盘控制系统、方法及相关组件 |
US20240295989A1 (en) * | 2023-03-02 | 2024-09-05 | Samsung Electronics Co., Ltd. | Nonvolatile memory package, storage device including the same, and method of operating the same |
CN117632035B (zh) * | 2023-12-13 | 2024-06-04 | 中国电子投资控股有限公司 | 一种数据存储方法、系统、存储介质及计算机设备 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09297707A (ja) * | 1996-05-08 | 1997-11-18 | Canon Inc | 記憶装置の駆動方法とその装置 |
JPH10320267A (ja) * | 1997-05-16 | 1998-12-04 | Canon Inc | メモリ制御装置及び方法 |
JP2001067303A (ja) * | 1999-08-24 | 2001-03-16 | Toshiba Corp | カード利用装置及び同装置におけるカード利用方法 |
US20070210174A1 (en) * | 2006-03-10 | 2007-09-13 | Lg Electronics Inc. | Method and apparatus for protocol selection on ICC |
US20080016269A1 (en) * | 2004-03-17 | 2008-01-17 | Super Talent Electronics Inc. | Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface |
US20090063761A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module Supporting Two Independent Memory Channels |
US20100162037A1 (en) * | 2008-12-22 | 2010-06-24 | International Business Machines Corporation | Memory System having Spare Memory Devices Attached to a Local Interface Bus |
JP2011507141A (ja) * | 2007-12-20 | 2011-03-03 | モサイド・テクノロジーズ・インコーポレーテッド | 二重機能対応の不揮発性メモリ素子 |
US20120072647A1 (en) * | 2010-09-17 | 2012-03-22 | Aplus Flash Technology, Inc. | Different types of memory integrated in one chip by using a novel protocol |
US8149862B1 (en) * | 2002-11-15 | 2012-04-03 | Netlogic Microsystems, Inc. | Multi-protocol communication circuit |
US20120221771A1 (en) * | 2011-02-25 | 2012-08-30 | Samsung Electronics Co., Ltd. | Data storage system and data mapping method of the same |
Family Cites Families (124)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6825698B2 (en) | 2001-08-29 | 2004-11-30 | Altera Corporation | Programmable high speed I/O interface |
US4914574A (en) | 1984-08-16 | 1990-04-03 | Mitsubishi Denki Kabushiki Kaisha | Data transmission apparatus having cascaded data processing modules for daisy chain data transfer |
US4723120A (en) | 1986-01-14 | 1988-02-02 | International Business Machines Corporation | Method and apparatus for constructing and operating multipoint communication networks utilizing point-to point hardware and interfaces |
US8027194B2 (en) | 1988-06-13 | 2011-09-27 | Samsung Electronics Co., Ltd. | Memory system and method of accessing a semiconductor memory device |
US5357621A (en) | 1990-09-04 | 1994-10-18 | Hewlett-Packard Company | Serial architecture for memory module control |
JP2601951B2 (ja) * | 1991-01-11 | 1997-04-23 | 株式会社東芝 | 半導体集積回路 |
US5430859A (en) | 1991-07-26 | 1995-07-04 | Sundisk Corporation | Solid state memory system including plural memory chips and a serialized bus |
US5404460A (en) | 1994-01-28 | 1995-04-04 | Vlsi Technology, Inc. | Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus |
US6072804A (en) | 1995-05-24 | 2000-06-06 | Thomson Consumer Electronics, Inc. | Ring bus data transfer system |
US5546023A (en) | 1995-06-26 | 1996-08-13 | Intel Corporation | Daisy chained clock distribution scheme |
US5742840A (en) | 1995-08-16 | 1998-04-21 | Microunity Systems Engineering, Inc. | General purpose, multiple precision parallel operation, programmable media processor |
JPH10154101A (ja) | 1996-11-26 | 1998-06-09 | Toshiba Corp | データ記憶システム及び同システムに適用するキャッシュ制御方法 |
US5929655A (en) | 1997-03-25 | 1999-07-27 | Adaptec, Inc. | Dual-purpose I/O circuit in a combined LINK/PHY integrated circuit |
US6253292B1 (en) | 1997-08-22 | 2001-06-26 | Seong Tae Jhang | Distributed shared memory multiprocessor system based on a unidirectional ring bus using a snooping scheme |
US6144576A (en) | 1998-08-19 | 2000-11-07 | Intel Corporation | Method and apparatus for implementing a serial memory architecture |
US6901457B1 (en) * | 1998-11-04 | 2005-05-31 | Sandisk Corporation | Multiple mode communications system |
US6271679B1 (en) | 1999-03-24 | 2001-08-07 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6381223B1 (en) | 1999-06-11 | 2002-04-30 | Trw Inc. | Ring-bus technology |
US7318117B2 (en) | 2004-02-26 | 2008-01-08 | Super Talent Electronics, Inc. | Managing flash memory including recycling obsolete sectors |
US7010642B2 (en) | 2000-01-05 | 2006-03-07 | Rambus Inc. | System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices |
US6535043B2 (en) | 2000-05-26 | 2003-03-18 | Lattice Semiconductor Corp | Clock signal selection system, method of generating a clock signal and programmable clock manager including same |
US6728798B1 (en) | 2000-07-28 | 2004-04-27 | Micron Technology, Inc. | Synchronous flash memory with status burst output |
US6625687B1 (en) | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US6658509B1 (en) | 2000-10-03 | 2003-12-02 | Intel Corporation | Multi-tier point-to-point ring memory interface |
US6373289B1 (en) | 2000-12-26 | 2002-04-16 | Intel Corporation | Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe |
EP1225597A1 (en) | 2001-01-15 | 2002-07-24 | STMicroelectronics S.r.l. | Synchronous-reading nonvolatile memory |
US6877079B2 (en) | 2001-03-06 | 2005-04-05 | Samsung Electronics Co., Ltd. | Memory system having point-to-point bus configuration |
CN100365965C (zh) * | 2001-05-08 | 2008-01-30 | 西门子公司 | 在具有并行级联编码及调制的多载波系统中传输数据的方法和装置 |
US7280549B2 (en) | 2001-07-09 | 2007-10-09 | Micron Technology, Inc. | High speed ring/bus |
US6625081B2 (en) | 2001-08-13 | 2003-09-23 | Micron Technology, Inc. | Synchronous flash memory with virtual segment architecture |
JP3799251B2 (ja) | 2001-08-24 | 2006-07-19 | エルピーダメモリ株式会社 | メモリデバイス及びメモリシステム |
JP3813849B2 (ja) * | 2001-09-14 | 2006-08-23 | 株式会社東芝 | カード装置 |
WO2004010315A1 (ja) | 2002-07-22 | 2004-01-29 | Renesas Technology Corp. | 半導体集積回路装置、データ処理システム及びメモリシステム |
US7373561B2 (en) | 2002-10-29 | 2008-05-13 | Broadcom Corporation | Integrated packet bit error rate tester for 10G SERDES |
US7093076B2 (en) | 2002-12-12 | 2006-08-15 | Samsung Electronics, Co., Ltd. | Memory system having two-way ring topology and memory device and memory module for ring-topology memory system |
US7308524B2 (en) | 2003-01-13 | 2007-12-11 | Silicon Pipe, Inc | Memory chain |
WO2004092904A2 (en) | 2003-04-10 | 2004-10-28 | Silicon Pipe, Inc. | Memory system having a multiplexed high-speed channel |
US7031221B2 (en) | 2003-12-30 | 2006-04-18 | Intel Corporation | Fixed phase clock and strobe signals in daisy chained chips |
US7723995B2 (en) * | 2004-02-27 | 2010-05-25 | Infineon Technologies Ag | Test switching circuit for a high speed data interface |
TWI271659B (en) * | 2004-05-05 | 2007-01-21 | Prolific Technology Inc | Memory card equipped with a multi-interface function and method for choosing a compatible transmission mode |
US7221613B2 (en) | 2004-05-26 | 2007-05-22 | Freescale Semiconductor, Inc. | Memory with serial input/output terminals for address and data and method therefor |
US7539800B2 (en) | 2004-07-30 | 2009-05-26 | International Business Machines Corporation | System, method and storage medium for providing segment level sparing |
US8375146B2 (en) | 2004-08-09 | 2013-02-12 | SanDisk Technologies, Inc. | Ring bus structure and its use in flash memory systems |
KR100579053B1 (ko) | 2004-08-26 | 2006-05-12 | 삼성전자주식회사 | 스마트 카드와 메모리 카드간의 멀티 인터페이스 방법 및멀티 인터페이스 카드 |
US7515174B1 (en) | 2004-12-06 | 2009-04-07 | Dreamworks Animation L.L.C. | Multi-user video conferencing with perspective correct eye-to-eye contact |
KR100621631B1 (ko) | 2005-01-11 | 2006-09-13 | 삼성전자주식회사 | 반도체 디스크 제어 장치 |
US7138823B2 (en) | 2005-01-20 | 2006-11-21 | Micron Technology, Inc. | Apparatus and method for independent control of on-die termination for output buffers of a memory device |
US7757037B2 (en) | 2005-02-16 | 2010-07-13 | Kingston Technology Corporation | Configurable flash memory controller and method of use |
US7371676B2 (en) | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US20070005831A1 (en) | 2005-06-30 | 2007-01-04 | Peter Gregorius | Semiconductor memory system |
JP5068754B2 (ja) | 2005-08-03 | 2012-11-07 | サンディスク テクノロジィース インコーポレイテッド | 改良されたホストインターフェイス |
TWI283074B (en) | 2005-08-17 | 2007-06-21 | Au Optronics Corp | TFD LCD panel |
KR100762259B1 (ko) | 2005-09-12 | 2007-10-01 | 삼성전자주식회사 | 버스트 읽기 레이턴시 기능을 갖는 낸드 플래시 메모리장치 |
US7966446B2 (en) | 2005-09-12 | 2011-06-21 | Samsung Electronics Co., Ltd. | Memory system and method having point-to-point link |
US8291295B2 (en) | 2005-09-26 | 2012-10-16 | Sandisk Il Ltd. | NAND flash memory controller exporting a NAND interface |
US7631245B2 (en) | 2005-09-26 | 2009-12-08 | Sandisk Il Ltd. | NAND flash memory controller exporting a NAND interface |
US7652922B2 (en) | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
US20070076502A1 (en) | 2005-09-30 | 2007-04-05 | Pyeon Hong B | Daisy chain cascading devices |
US20070165457A1 (en) | 2005-09-30 | 2007-07-19 | Jin-Ki Kim | Nonvolatile memory system |
TWI446356B (zh) | 2005-09-30 | 2014-07-21 | Mosaid Technologies Inc | 具有輸出控制之記憶體及其系統 |
US7747833B2 (en) | 2005-09-30 | 2010-06-29 | Mosaid Technologies Incorporated | Independent link and bank selection |
KR100660546B1 (ko) | 2005-11-10 | 2006-12-22 | 삼성전자주식회사 | 반도체 디스크 제어 장치 |
US8364861B2 (en) | 2006-03-28 | 2013-01-29 | Mosaid Technologies Incorporated | Asynchronous ID generation |
US8069328B2 (en) | 2006-03-28 | 2011-11-29 | Mosaid Technologies Incorporated | Daisy chain cascade configuration recognition technique |
US8335868B2 (en) | 2006-03-28 | 2012-12-18 | Mosaid Technologies Incorporated | Apparatus and method for establishing device identifiers for serially interconnected devices |
US7551492B2 (en) | 2006-03-29 | 2009-06-23 | Mosaid Technologies, Inc. | Non-volatile semiconductor memory with page erase |
US20070245061A1 (en) | 2006-04-13 | 2007-10-18 | Intel Corporation | Multiplexing a parallel bus interface and a flash memory interface |
US7366028B2 (en) | 2006-04-24 | 2008-04-29 | Sandisk Corporation | Method of high-performance flash memory data transfer |
US7904639B2 (en) | 2006-08-22 | 2011-03-08 | Mosaid Technologies Incorporated | Modular command structure for memory and memory system |
US7752364B2 (en) | 2006-12-06 | 2010-07-06 | Mosaid Technologies Incorporated | Apparatus and method for communicating with semiconductor devices of a serial interconnection |
US7925854B2 (en) | 2006-12-06 | 2011-04-12 | Mosaid Technologies Incorporated | System and method of operating memory devices of mixed type |
US8010709B2 (en) | 2006-12-06 | 2011-08-30 | Mosaid Technologies Incorporated | Apparatus and method for producing device identifiers for serially interconnected devices of mixed type |
US7529149B2 (en) | 2006-12-12 | 2009-05-05 | Mosaid Technologies Incorporated | Memory system and method with serial and parallel modes |
US7554855B2 (en) | 2006-12-20 | 2009-06-30 | Mosaid Technologies Incorporated | Hybrid solid-state memory system having volatile and non-volatile memory |
US7650459B2 (en) | 2006-12-21 | 2010-01-19 | Intel Corporation | High speed interface for non-volatile memory |
CN101617371B (zh) | 2007-02-16 | 2014-03-26 | 莫塞德技术公司 | 具有多个外部电源的非易失性半导体存储器 |
US8046527B2 (en) | 2007-02-22 | 2011-10-25 | Mosaid Technologies Incorporated | Apparatus and method for using a page buffer of a memory device as a temporary cache |
US8086785B2 (en) | 2007-02-22 | 2011-12-27 | Mosaid Technologies Incorporated | System and method of page buffer operation for memory devices |
US7865756B2 (en) | 2007-03-12 | 2011-01-04 | Mosaid Technologies Incorporated | Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices |
US7916557B2 (en) | 2007-04-25 | 2011-03-29 | Micron Technology, Inc. | NAND interface |
US7688652B2 (en) | 2007-07-18 | 2010-03-30 | Mosaid Technologies Incorporated | Storage of data in memory via packet strobing |
US20090043946A1 (en) | 2007-08-09 | 2009-02-12 | Webb Randall K | Architecture for very large capacity solid state memory systems |
TWI376603B (en) | 2007-09-21 | 2012-11-11 | Phison Electronics Corp | Solid state disk storage system with a parallel accessing architecture and a solid state disk controller |
US8397011B2 (en) | 2007-10-05 | 2013-03-12 | Joseph Ashwood | Scalable mass data storage device |
US7913033B2 (en) | 2007-10-09 | 2011-03-22 | Micron Technology, Inc. | Non-volatile memory device having assignable network identification |
US7889578B2 (en) | 2007-10-17 | 2011-02-15 | Mosaid Technologies Incorporated | Single-strobe operation of memory devices |
US8825939B2 (en) | 2007-12-12 | 2014-09-02 | Conversant Intellectual Property Management Inc. | Semiconductor memory device suitable for interconnection in a ring topology |
US7660177B2 (en) | 2007-12-21 | 2010-02-09 | Silicon Storage Technology, Inc. | Non-volatile memory device having high speed serial interface |
WO2009079744A1 (en) | 2007-12-21 | 2009-07-02 | Mosaid Technologies Incorporated | Non-volatile semiconductor memory device with power saving feature |
US7934052B2 (en) | 2007-12-27 | 2011-04-26 | Pliant Technology, Inc. | System and method for performing host initiated mass storage commands using a hierarchy of data structures |
JP4519923B2 (ja) | 2008-02-29 | 2010-08-04 | 株式会社東芝 | メモリシステム |
JP4498426B2 (ja) | 2008-03-01 | 2010-07-07 | 株式会社東芝 | メモリシステム |
US7920431B2 (en) | 2008-06-02 | 2011-04-05 | Micron Technology, Inc. | Asynchronous/synchronous interface |
TWI473097B (zh) | 2008-06-02 | 2015-02-11 | A Data Technology Co Ltd | 自動切換記憶體介面模式之快閃記憶體裝置 |
JP5253901B2 (ja) | 2008-06-20 | 2013-07-31 | 株式会社東芝 | メモリシステム |
US8139390B2 (en) | 2008-07-08 | 2012-03-20 | Mosaid Technologies Incorporated | Mixed data rates in memory devices and systems |
US7969801B2 (en) | 2008-07-17 | 2011-06-28 | Hynix Semiconductor Inc. | Data input circuit and nonvolatile memory device including the same |
US8181056B2 (en) | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
US8161313B2 (en) | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
US8069300B2 (en) | 2008-09-30 | 2011-11-29 | Micron Technology, Inc. | Solid state storage device controller with expansion mode |
US8214579B2 (en) | 2008-09-30 | 2012-07-03 | Tdk Corporation | Memory controller, flash memory system with memory controller, and method of controlling flash memory |
US8244937B2 (en) | 2008-09-30 | 2012-08-14 | Micron Technology, Inc. | Solid state storage device controller with parallel operation mode |
US8134852B2 (en) | 2008-10-14 | 2012-03-13 | Mosaid Technologies Incorporated | Bridge device architecture for connecting discrete memory devices to a system |
US7957173B2 (en) | 2008-10-14 | 2011-06-07 | Mosaid Technologies Incorporated | Composite memory having a bridging device for connecting discrete memory devices to a system |
US8161354B2 (en) | 2008-10-16 | 2012-04-17 | Genesys Logic, Inc. | Flash memory controller having configuring unit for error correction code (ECC) capability and method thereof |
US8200925B2 (en) | 2008-10-31 | 2012-06-12 | Mosaid Technologies Incorporated | Data mirroring in serial-connected memory system |
KR101014149B1 (ko) | 2008-11-13 | 2011-02-14 | (주)인디링스 | 메모리 뱅크로의 접근을 제어하는 고체 상태 디스크를 위한컨트롤러 |
US20100161914A1 (en) * | 2008-12-23 | 2010-06-24 | Eilert Sean S | Autonomous memory subsystems in computing platforms |
JP5317690B2 (ja) | 2008-12-27 | 2013-10-16 | 株式会社東芝 | メモリシステム |
US8078848B2 (en) | 2009-01-09 | 2011-12-13 | Micron Technology, Inc. | Memory controller having front end and back end channels for modifying commands |
KR101006748B1 (ko) | 2009-01-29 | 2011-01-10 | (주)인디링스 | 패드들의 동시 스위칭을 제어하는 고체 상태 디스크를 위한컨트롤러 |
US8566508B2 (en) | 2009-04-08 | 2013-10-22 | Google Inc. | RAID configuration in a flash memory data storage device |
US8151051B2 (en) | 2009-04-23 | 2012-04-03 | International Business Machines Corporation | Redundant solid state disk system via interconnect cards |
US20100287329A1 (en) * | 2009-05-06 | 2010-11-11 | Apple Inc. | Partial Page Operations for Non-Volatile Memory Systems |
US8271697B2 (en) | 2009-09-29 | 2012-09-18 | Micron Technology, Inc. | State change in systems having devices coupled in a chained configuration |
US8214580B2 (en) | 2009-10-23 | 2012-07-03 | International Business Machines Corporation | Solid state drive with adjustable drive life and capacity |
US8595411B2 (en) | 2009-12-30 | 2013-11-26 | Sandisk Technologies Inc. | Method and controller for performing a sequence of commands |
US8582382B2 (en) | 2010-03-23 | 2013-11-12 | Mosaid Technologies Incorporated | Memory system having a plurality of serially connected devices |
US7888966B1 (en) | 2010-03-25 | 2011-02-15 | Sandisk Corporation | Enhancement of input/output for non source-synchronous interfaces |
US20110258366A1 (en) | 2010-04-19 | 2011-10-20 | Mosaid Technologies Incorporated | Status indication in a system having a plurality of memory devices |
US8843692B2 (en) | 2010-04-27 | 2014-09-23 | Conversant Intellectual Property Management Inc. | System of interconnected nonvolatile memories having automatic status packet |
CN102971795A (zh) | 2010-05-07 | 2013-03-13 | 莫塞德技术公司 | 使用单个缓冲区同时读取多个存储器装置的方法和设备 |
JP2012174143A (ja) | 2011-02-23 | 2012-09-10 | Toshiba Corp | 記憶装置及びその制御方法 |
-
2013
- 2013-03-15 US US13/835,968 patent/US9471484B2/en active Active
- 2013-09-18 KR KR1020147036998A patent/KR102113359B1/ko active IP Right Grant
- 2013-09-18 JP JP2015531407A patent/JP6386460B2/ja not_active Expired - Fee Related
- 2013-09-18 WO PCT/CA2013/000782 patent/WO2014043788A1/en active Application Filing
- 2013-09-18 CN CN201380048582.4A patent/CN104704563B/zh not_active Expired - Fee Related
- 2013-09-18 TW TW102133883A patent/TWI595488B/zh not_active IP Right Cessation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09297707A (ja) * | 1996-05-08 | 1997-11-18 | Canon Inc | 記憶装置の駆動方法とその装置 |
JPH10320267A (ja) * | 1997-05-16 | 1998-12-04 | Canon Inc | メモリ制御装置及び方法 |
JP2001067303A (ja) * | 1999-08-24 | 2001-03-16 | Toshiba Corp | カード利用装置及び同装置におけるカード利用方法 |
US8149862B1 (en) * | 2002-11-15 | 2012-04-03 | Netlogic Microsystems, Inc. | Multi-protocol communication circuit |
US20080016269A1 (en) * | 2004-03-17 | 2008-01-17 | Super Talent Electronics Inc. | Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface |
US20070210174A1 (en) * | 2006-03-10 | 2007-09-13 | Lg Electronics Inc. | Method and apparatus for protocol selection on ICC |
US20090063761A1 (en) * | 2007-08-31 | 2009-03-05 | Gower Kevin C | Buffered Memory Module Supporting Two Independent Memory Channels |
JP2011507141A (ja) * | 2007-12-20 | 2011-03-03 | モサイド・テクノロジーズ・インコーポレーテッド | 二重機能対応の不揮発性メモリ素子 |
US20100162037A1 (en) * | 2008-12-22 | 2010-06-24 | International Business Machines Corporation | Memory System having Spare Memory Devices Attached to a Local Interface Bus |
US20120072647A1 (en) * | 2010-09-17 | 2012-03-22 | Aplus Flash Technology, Inc. | Different types of memory integrated in one chip by using a novel protocol |
US20120221771A1 (en) * | 2011-02-25 | 2012-08-30 | Samsung Electronics Co., Ltd. | Data storage system and data mapping method of the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019160307A (ja) * | 2018-03-09 | 2019-09-19 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 適応型インターフェイスストレージ装置 |
JP7206130B2 (ja) | 2018-03-09 | 2023-01-17 | 三星電子株式会社 | 適応型インターフェイスストレージ装置 |
US11775462B2 (en) | 2018-03-09 | 2023-10-03 | Samsung Electronics Co., Ltd. | Adaptive interface storage device with multiple storage protocols including NVMe and NVMe over fabrics storage devices |
Also Published As
Publication number | Publication date |
---|---|
CN104704563B (zh) | 2018-02-16 |
KR20150070049A (ko) | 2015-06-24 |
CN104704563A (zh) | 2015-06-10 |
TWI595488B (zh) | 2017-08-11 |
TW201428748A (zh) | 2014-07-16 |
JP6386460B2 (ja) | 2018-09-05 |
KR102113359B1 (ko) | 2020-05-21 |
US20140082260A1 (en) | 2014-03-20 |
US9471484B2 (en) | 2016-10-18 |
WO2014043788A1 (en) | 2014-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6386460B2 (ja) | デュアルモードピン配列を有するフラッシュメモリコントローラ | |
US20140122777A1 (en) | Flash memory controller having multi mode pin-out | |
US10031879B2 (en) | Memory device for a hierarchical memory architecture | |
WO2014153640A1 (en) | Asynchronous bridge chip | |
TW201032053A (en) | A bridging device having a virtual page buffer | |
US10691338B2 (en) | Data storage device and data processing system including same | |
US9977735B2 (en) | Data storage device and operating method thereof | |
US11625342B2 (en) | Link startup method of storage device, and storage device, host and system implementing same | |
US8883521B2 (en) | Control method of multi-chip package memory device | |
US20220066689A1 (en) | Storage device for performing high-speed link startup and storage system including the same | |
CN113111024A (zh) | 存储装置、存储系统和及操作存储装置的方法 | |
US20230007903A1 (en) | Storage device and method of operation thereof | |
US9728234B1 (en) | Operating method of semiconductor memory device | |
TWI597728B (zh) | 指派半導體晶粒以致能高堆疊能力之技術 | |
US20140156882A1 (en) | Memory device, operating method thereof, and data storage device including the same | |
US11934691B2 (en) | Storage device for high speed link startup and storage system including the same | |
US20240127869A1 (en) | Storage devices having multi drop structure | |
US10706001B2 (en) | Modular and scalable PCIe controller architecture | |
US20170212816A1 (en) | Semiconductor memory device and data storage device including the same | |
CN114300010A (zh) | 存储控制器、存储系统及其操作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150519 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150226 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20150304 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20150212 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150728 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160616 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170324 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170329 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20170614 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20170719 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20170724 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20170719 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171219 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20180319 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20180517 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180619 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180724 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180809 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6386460 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |