JP2015115342A - 電子部品実装装置及びそれを備える半導体装置 - Google Patents
電子部品実装装置及びそれを備える半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 84
- 239000002184 metal Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 230000007547 defect Effects 0.000 claims description 13
- 230000008646 thermal stress Effects 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000012217 deletion Methods 0.000 description 3
- 230000037430 deletion Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置の構成を示す上面図であり、図2は、当該構成を図1のA1−A1線に沿って示す断面図であり、図3は、当該構成を図1のB1−B1線に沿って示す断面図である。
図4は、本発明の実施の形態2に係る半導体装置の構成を示す上面図であり、図5は、当該構成を図4のA2−A2線に沿って示す断面図であり、図6は、当該構成を図4のB2−B2線に沿って示す断面図である。なお、本実施の形態2に係る半導体装置において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる点を中心に以下説明する。
図7は、本発明の実施の形態3に係る半導体装置の構成を示す上面図であり、図8は、当該構成を図7のA3−A3線に沿って示す断面図であり、図9は、当該構成を図7のB3−B3線に沿って示す断面図である。なお、本実施の形態3に係る半導体装置において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる点を中心に以下説明する。
図10は、本発明の実施の形態4に係る半導体装置の構成を示す上面図であり、図11は、当該構成を図10のA4−A4線に沿って示す断面図であり、図12は、当該構成を図10のB4−B4線に沿って示す断面図である。なお、本実施の形態4に係る半導体装置において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる点を中心に以下説明する。
図13は、本発明の実施の形態5に係る半導体装置の構成を示す上面図であり、図14は、当該構成を図13のA5−A5線に沿って示す断面図であり、図15は、当該構成を図10のB5−B5線に沿って示す断面図である。なお、本実施の形態5に係る半導体装置において、以上で説明した構成要素と同一または類似するものについては同じ参照符号を付し、異なる点を中心に以下説明する。
Claims (9)
- 金属パターンが形成された絶縁基板と、
メルフ型電子部品と
を備え、
前記金属パターンと前記金属パターンの欠損部から露出された前記絶縁基板とにより構成される第1受け部、または、前記金属パターンの欠損部により分離された前記金属パターンの互いに対向する側部の上部に形成された窪みにより構成される第2受け部に、前記メルフ型電子部品が嵌合され、
前記メルフ型電子部品と前記金属パターンとの間に形成された導電性部材をさらに備え、
前記導電性部材は、
前記メルフ型電子部品と前記絶縁基板との間に形成されない、電子部品実装装置。 - 請求項1に記載の電子部品実装装置であって、
前記第1受け部は、
平面視において十字に切られて4つに分離された前記金属パターンの互いに対向する側部と、前記金属パターンの前記欠損部から露出された前記絶縁基板とから形成され、
前記導電性部材は、
前記メルフ型電子部品と前記絶縁基板とが接触された状態で、前記メルフ型電子部品と前記金属パターンの前記側部とを接合する、電子部品実装装置。 - 請求項1に記載の電子部品実装装置であって、
前記メルフ型電子部品と前記絶縁基板との間に空隙を設けた状態で、前記メルフ型電子部品と前記金属パターンとを接合する、電子部品実装装置。 - 請求項3に記載の電子部品実装装置であって、
前記第1受け部は、
平面視において十字に切られて2つに分離された前記金属パターンの互いに対向する側部と、前記金属パターンの前記欠損部から露出された前記絶縁基板とから形成され、
前記導電性部材は、
前記メルフ型電子部品と前記金属パターンの前記側部及びその上部とを接合する、電子部品実装装置。 - 請求項3に記載の電子部品実装装置であって、
前記第1受け部は、
平面視において十字に切られて4つに分離された前記金属パターンの互いに対向する側部と、前記金属パターンの前記欠損部から露出された前記絶縁基板とから形成され、
前記導電性部材は、
前記メルフ型電子部品と前記金属パターンの前記側部及びその上部とを接合する、電子部品実装装置。 - 請求項1または請求項3に記載の電子部品実装装置であって、
前記導電性部材は、
前記メルフ型電子部品と前記金属パターンの前記第2受け部の前記窪みの内部とを接合する、電子部品実装装置。 - 請求項1から請求項6のいずれか1項に記載の電子部品実装装置であって、
複数の前記導電性部材同士の間に位置する前記絶縁基板の表面上に、切り欠き部が形成された、電子部品実装装置。 - 請求項1から請求項7のいずれか1項に記載の電子部品実装装置と、
前記絶縁基板上に実装された電力半導体素子と
を備える、半導体装置。 - 請求項8に記載の半導体装置であって、
前記電力半導体素子の材質はワイドバンドギャップ半導体を含む、半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013253978A JP6289063B2 (ja) | 2013-12-09 | 2013-12-09 | 電子部品実装装置及びそれを備える半導体装置 |
US14/452,785 US9723718B2 (en) | 2013-12-09 | 2014-08-06 | Electronic component mounting device and semiconductor device including the same |
DE102014222601.5A DE102014222601B4 (de) | 2013-12-09 | 2014-11-05 | Vorrichtung mit montierten elektronischen Komponenten und Halbleitervorrichtung mit derselben |
CN201410747912.5A CN104703406B (zh) | 2013-12-09 | 2014-12-09 | 电子部件安装装置及具备电子部件安装装置的半导体装置 |
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US9723718B2 (en) | 2017-08-01 |
JP6289063B2 (ja) | 2018-03-07 |
DE102014222601A1 (de) | 2015-06-11 |
CN104703406B (zh) | 2018-01-19 |
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