WO2013132644A1 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- WO2013132644A1 WO2013132644A1 PCT/JP2012/056078 JP2012056078W WO2013132644A1 WO 2013132644 A1 WO2013132644 A1 WO 2013132644A1 JP 2012056078 W JP2012056078 W JP 2012056078W WO 2013132644 A1 WO2013132644 A1 WO 2013132644A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plate
- insulating member
- chip
- heat sink
- facing
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
Definitions
- the present invention relates to a semiconductor module.
- a power semiconductor chip, an insulating substrate, and a heat sink are stacked.
- the insulating substrate is formed of a plate-like insulating member having metal layers on both main surfaces
- the power semiconductor chip is joined to one metal layer
- the heat sink is joined to the other metal layer.
- the one metal layer is formed in a predetermined pattern having a portion for providing a wiring as well as a portion to which the power semiconductor chip is bonded.
- the heat sink is made of, for example, a metal such as copper.
- the heat sink forms a capacitive electrical connection with the power semiconductor chip through the plate-like insulating member, and the above-mentioned wiring (one of the above-mentioned wiring on the plate-like insulating member as described above). (Provided by the metal layer) also form a capacitive electrical connection. Therefore, the power semiconductor chip and the wiring are capacitively coupled through the plate-like insulating member and the heat sink.
- Such capacitive coupling may be, for example, a path for transmitting noise associated with switching of the power semiconductor chip to the wiring. If the noise transmitted to the wiring is applied from the wiring to the power semiconductor chip, there is a concern that the power semiconductor module may malfunction.
- the capacitive coupling between the power semiconductor chip and the wiring can be reduced by thickening the plate-like insulating member. That is, the insulation between the power semiconductor chip and the wiring can be improved. However, if the plate-like insulating member is thickened, the thermal resistance is increased, and therefore the heat dissipation of the power semiconductor chip is reduced.
- capacitive coupling via the plate-like insulating member and the heat sink may be formed also between a plurality of power semiconductor chips, and in this case, the same problem as described above may occur.
- a semiconductor module is provided with a conductive heat sink, a power semiconductor chip provided on the side of the predetermined surface of the heat sink, and the side of the predetermined surface of the heat sink, the power semiconductor A low power portion having lower power consumption than a chip, a first plate-like insulating member extending between the power semiconductor chip and the heat sink, and a portion extending between the low power portion and the heat sink And a second plate-like insulating member.
- the portion of the second plate-shaped insulating member facing the low power portion is thicker than the portion of the first plate-shaped insulating member facing the power semiconductor chip.
- the heat resistance under the power semiconductor chip can be reduced by the first plate-shaped insulating member, and the heat dissipation can be ensured.
- the second plate-like insulating member can reduce capacitive coupling between the power semiconductor chip and the low power part through the first and second plate-like insulating members and the heat sink, thereby reducing the power semiconductor chip and the low power.
- the insulation between the power unit can be secured.
- FIG. 1 is a cross-sectional view illustrating a semiconductor module according to a first embodiment
- FIG. 1 is a top view illustrating a semiconductor module according to a first embodiment
- FIG. 7 is a cross-sectional view illustrating a semiconductor module according to a second embodiment
- FIG. 18 is a cross-sectional view illustrating a semiconductor module according to a modification of the second embodiment
- FIG. 16 is a cross-sectional view illustrating a semiconductor module according to a modification of the first embodiment
- FIG. 18 is a cross-sectional view illustrating a semiconductor module according to a third embodiment
- FIG. 18 is a cross-sectional view illustrating a semiconductor module according to a fourth embodiment
- FIG. 26 is a cross-sectional view illustrating a semiconductor module according to a fifth embodiment
- FIG. 26 is a cross-sectional view illustrating a semiconductor module according to a sixth embodiment
- FIG. 33 is a cross-sectional view illustrating a semiconductor module according to a seventh embodiment
- FIG. 33 is a cross-sectional view illustrating a semiconductor module according to an eighth embodiment
- FIG. 1 illustrates a cross-sectional view of a power semiconductor module (hereinafter also referred to as a semiconductor module) 1 according to the first embodiment.
- the semiconductor module 1 includes power semiconductor chips (hereinafter also referred to as semiconductor chips) 10a and 20b, plate-like insulating members 30ab and 30c, metal layers 40ab, 50ab, 40c and 50c, and a heat sink 60, joint members 72a, 72b, 74ab, 74c, and connection members 82, 84, 86.
- power semiconductor chips hereinafter also referred to as semiconductor chips
- Power semiconductor chip 10a has chip main surfaces 11 and 12 which are in a relation of front and back (in other words, they face each other through the chip inside), and power semiconductor chip 20b also has chip main surfaces 21 and 22 similarly There is. 1, the chip main surfaces 11 and 21 are also referred to as chip upper surfaces (or upper surfaces) 11 and 21, and the chip main surfaces 12 and 22 are also referred to as chip lower surfaces (or lower surfaces) 12 and 22.
- the material of the semiconductor chips 10a and 20b is, for example, silicon (Si), but one or both of the semiconductor chips 10a and 20b are other materials, for example, so-called wide band gap materials such as silicon carbide (SiC) and gallium nitride (GaN) May be composed of
- power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes are formed.
- the semiconductor chips 10a and 20b may be the same type of device or different types of devices.
- an emitter electrode and a gate electrode of the IGBT are provided on the chip upper surface 11, and a collector electrode of the IGBT is provided on the chip lower surface 12.
- connection member 82 is a bonding wire in the example of FIG. 1, but a conductive plate or the like may be used.
- the chip lower surfaces 12 and 22 are bonded to a metal layer 40ab provided on a plate-like insulating member 30ab by bonding members 72a and 72b such as solder.
- the plate-like insulating member 30ab has main surfaces 31ab and 32ab which are in the relation of front and back.
- the main surface 31ab is also referred to as an upper surface 31ab
- the main surface 32ab is also referred to as a lower surface 32ab in accordance with the illustration of FIG.
- the case where the main surfaces 31ab and 32ab are flat and parallel to each other is exemplified.
- the thickness of the plate-like insulating member 30ab is uniform over the entire member.
- the plate-like insulating member 30ab is made of, for example, an insulating material such as an epoxy resin filled with a filler or a ceramic.
- the metal layer 40ab is joined to the upper surface 31ab of the plate-like insulating member 30ab, and the metal layer 50ab is joined to the lower surface 32ab of the plate-like insulating member 30ab.
- the metal layers 40ab and 50ab are made of, for example, copper or the like.
- the metal layers 40ab and 50ab function as a base of bonding by the bonding members 72a, 72b and 74ab such as solder.
- the metal layer 40ab also functions as a wire connecting the electrodes of the chip lower surfaces 12 and 22 to each other. Materials other than metal may be adopted as long as these functions can be realized.
- the laminated body of plate-shaped insulating member 30ab and metal layer 40ab and 50ab may be called an insulating substrate.
- the plate-like insulating member 30c has main surfaces 31c and 32c in a relationship of front and back.
- the main surface 31c is also referred to as the upper surface 31c
- the main surface 32c is also referred to as the lower surface 32c in accordance with the illustration of FIG.
- the case where the main surfaces 31c and 32c are flat and parallel to each other is exemplified.
- the thickness of the plate-like insulating member 30c is uniform over the entire member.
- the plate-like insulating member 30c is made of, for example, the same material as the plate-like insulating member 30ab.
- the metal layer 40c is joined to the upper surface 31c of the plate-like insulating member 30c, and the metal layer 50c is joined to the lower surface 32c of the plate-like insulating member 30c.
- the metal layers 40c and 50c are made of, for example, the same material as the metal layers 40ab and 50ab.
- the metal layer 40c is formed in a predetermined wiring pattern, and hence the metal layer 40c may be referred to as a wiring layer 40c, a wiring pattern 40c, or the like.
- the wiring layer 40c may be made of a conductive material other than metal.
- the wiring pattern by the metal layer 40c has three wiring portions 41, 42 and 43, and the wiring portions 42 and 43 are connected to the top surface 11 of the semiconductor chip 10a by connection members 84 and 86.
- the connection members 84 and 86 are bonding wires in the example of FIG. 1, but conductive plate materials or the like may be used.
- the metal layer 50c functions as a base of bonding by the bonding member 74c such as solder, and materials other than metal may be adopted if such a function can be realized.
- the laminated body of the plate-shaped insulating member 30c and the metal layers 40c and 50c may be called an insulating substrate.
- the heat sink 60 is made of, for example, a conductive material such as copper.
- the heat sink 60 has a plate shape in the example of FIG. 1 and has main surfaces 61 and 62 which are in the relation of front and back.
- the main surface 61 is also referred to as the upper surface 61 and the main surface 62 is also referred to as the lower surface 62 in accordance with the illustration of FIG. 1.
- the lower surface 62 may be fin-shaped.
- Plate-shaped insulating members 30ab and 30c are mounted on the upper surface 61 of the heat sink 60. Specifically, the metal layer 50ab provided on the lower surface 32ab of the plate-like insulating member 30ab is joined to the upper surface 61 of the heat sink 60 by the joining member 74ab, and the metal layer provided on the lower surface 32c of the plate-like insulating member 30c 50c are joined to the upper surface 61 of the heat sink 60 by a joining member 74c.
- the bonding members 74ab and 74c are, for example, solders. According to this, the upper surface 61 of the heat sink 60 and the lower surfaces 32ab and 32c of the plate-like insulating members 30ab and 30c face each other.
- the configuration on the upper surface 61 of the heat sink 60 is accommodated in a sealing member such as a case, a sealing resin, etc. not shown. However, the lower surface 62 of the heat sink 60 is exposed from the sealing member. In addition, the external terminal not shown is pulled out from a sealing member.
- the semiconductor module 1 may include only one semiconductor chip, or may include three or more semiconductor chips.
- the semiconductor chip 20b, the bonding member 72b, and the connection member 82 are omitted from the example of FIG.
- the top view illustrated in FIG. 2 three combinations of the semiconductor chips 10a and 20b are illustrated.
- three wiring portions 42 are provided on the plate-like insulating member 30 c, and the balance resistors 44 are connected between the wiring portions 42 and the wiring portions 41.
- the component 90 c disposed on the upper surface 31 c of the plate-like insulating member 30 c (the wiring layer 40 c is included in the example of FIG.
- the resistor 44 is included) has lower power consumption (in other words, power to be handled) compared to the semiconductor chips 10a and 20b. Therefore, the component 90c is also referred to as a low power unit 90c.
- the low power part 90c is a part which supplies a predetermined signal (for example, a control signal such as a gate signal) to the semiconductor chip 10a in the example of FIG. 1 and FIG.
- the signal supply unit may include, for example, various circuits (for example, a circuit that generates a control signal for the semiconductor chip 10a from an external input signal).
- the low power unit 90c may include, in addition to or in place of the above signal supply unit, a signal acquisition portion for acquiring a predetermined signal (for example, a signal related to chip temperature) from one or both of the semiconductor chips 10a and 20b.
- the low power unit 90c may further include, for example, a pad unit (which can be formed by the metal layer 40c) to which an external terminal is connected, or may include only such a pad unit.
- connection between the external terminals and the semiconductor chips 10a and 20b can also be realized by direct bonding or indirect connection through bonding wires or the like without using the pad portion in the low power portion 90c. It is.
- the low power portion 90c can adopt various configurations, but as described above, the power consumption is lower than the semiconductor chips 10a and 20b, and thus the heat generation is smaller than the semiconductor chips 10a and 20b.
- both the semiconductor chips 10 a and 20 b and the low power portion 90 c are provided on the upper surface 61 side of the heat sink 60, and a plate shape is provided between the semiconductor chips 10 a and 20 b and the heat sink 60.
- the insulating member 30 ab extends, and the plate-like insulating member 30 c extends between the low power portion 90 c and the heat sink 60.
- the thickness tc of the portion 33c facing the low power portion 90c in the plate-like insulating member 30c is smaller than the thickness tab of the portion 33ab facing the semiconductor chips 10a and 20b in the plate-like insulating member 30ab. Large (tc> tab).
- the thermal resistance under the semiconductor chips 10a and 20b can be reduced by the thin plate-like insulating members 30ab for the semiconductor chips 10a and 20b. Therefore, the heat dissipation of the semiconductor chips 10a and 20b can be secured. Furthermore, in view of the fact that the low power portion 90c generates less heat than the semiconductor chips 10a and 20b, by adopting a thick plate-like insulating member 30c for the low power portion 90c, the plate-like insulating members 30ab and 30c and the heat sink 60 Capacitive coupling between the semiconductor chips 10a and 20b and the low power unit 90c. Therefore, the insulation between the semiconductor chips 10a and 20b and the low power unit 90c can be secured. Thus, according to the semiconductor module 1, both heat dissipation and insulation can be ensured.
- plate-like insulating members 30ab and 30c are separated in the example of FIG. 1, these plate-like insulating members 30ab and 30c may be in contact with each other. Such a modification can be applied to various semiconductor modules described later.
- FIG. 3 illustrates a cross-sectional view of the semiconductor module 1B according to the second embodiment.
- the semiconductor module 1B has a configuration in which the plate-like insulating members 30ab and 30c in the semiconductor module 1 (see FIG. 1) exemplified in the first embodiment are changed to a plate-like insulating member 30abc.
- the other configuration of the semiconductor module 1B is basically the same as that of the semiconductor module 1 described above.
- the plate-like insulating member 30abc roughly corresponds to a member obtained by integrating the plate-like insulating members 30ab and 30c (see FIG. 1) exemplified in the first embodiment. That is, the plate-like insulating member 30 abc extends between the semiconductor chips 10 a and 20 b and the heat sink 60 and also extends between the low power portion 90 c and the heat sink 60.
- the plate-like insulating member 30abc has main surfaces 31abc and 32abc which are in a relation of front and back.
- the main surface 31abc is also referred to as an upper surface 31abc
- the main surface 32abc is also referred to as a lower surface 32abc in accordance with the illustration of FIG. 3.
- the thickness tc of the portion 33c facing the low power portion 90c is larger than the thickness tab of the portion 33ab facing the semiconductor chips 10a and 20b (tc> tab).
- the region facing the semiconductor chips 10a and 20b is located closer to the lower surface 32abc than the region facing the low power portion 90c. In the example of FIG. 3, both regions are flat.
- the lower surface 32abc of the plate-like insulating member 30abc is flat in the example of FIG. Due to the shape of the upper surface 31abc and the lower surface 32abc, different thicknesses are formed in the common plate-like insulating member 30abc.
- Such difference in thickness can be formed, for example, by rolling the plate-like insulation member before hardening in two steps. Specifically, the plate-like insulating member before hardening is first rolled to the thickness of the thick portion 33c, and then, the predetermined portion is rolled again to the thickness of the thin portion 33ab.
- both heat dissipation and insulation can be ensured.
- the thermal resistance under the semiconductor chips 10a and 20b can be reduced by the thin portions 33ab facing the semiconductor chips 10a and 20b in the plate-like insulating member 30abc. Therefore, the heat dissipation of the semiconductor chips 10a and 20b can be secured.
- capacitive coupling between the semiconductor chips 10a and 20b and the low power portion 90c via the plate insulating member 30abc and the heat sink 60 by the thick portion 33c facing the low power portion 90c in the plate insulating member 30abc. Can be reduced. Therefore, the insulation between the semiconductor chips 10a and 20b and the low power unit 90c can be secured.
- the metal layers 50ab and 50c on the lower surface 32ab side of the plate-like insulating member 30abc can be changed to a continuous metal layer.
- the joining members 74ab and 74c can also be changed to a series of joining members. Such a modification can be applied to various semiconductor modules described later.
- the semiconductor module 1B illustrated in FIG. 3 has a projecting portion 34 at the end of the upper surface 31abc of the plate-like insulating member 30abc.
- the projecting portion 34 is provided to surround the thin portion 33ab facing the semiconductor chips 10a and 20b.
- the thickness of the protrusion part 34 is set to tc in the example of FIG. 3, it is not limited to this example.
- the projecting portion 34 can be omitted.
- the protruding portion 34 it is possible to increase the creeping distance between the upper surface 31abc side and the lower surface 32abc side of the thin portion 33ab (the distance through the end face of the plate-like insulating member 30abc). For this reason, it is possible to secure the insulation of the creepage between the electric potential on the upper surface 31ab side and the electric potential on the lower surface 32abc side.
- the shape of the plate-like insulating member 30abc is simplified, and the manufacture of the plate-like insulating member 30abc is facilitated.
- the projecting portion 34 can also be adopted to the semiconductor module 1 exemplified in the first embodiment.
- FIG. 5 illustrates a semiconductor module 1D to which such a modification is added.
- the projecting portion 34 is provided at the end of the upper surface 31ab of the plate-like insulating member 30ab for the semiconductor chips 10a and 20b.
- Embodiment 3 semiconductor chips made of so-called wide band gap materials such as silicon carbide (SiC) and gallium nitride (GaN) are capable of high-temperature operation compared to semiconductor chips made of silicon (Si).
- the wide band gap semiconductor provides a chip with high heat resistance.
- a semiconductor module in which semiconductor chips having different heat resistances are mixed will be described.
- the semiconductor chip with higher heat resistance is also referred to as a high heat resistance chip
- the semiconductor chip with lower heat resistance is also referred to as a low heat resistance chip for the sake of convenience.
- FIG. 6 illustrates a cross-sectional view of a semiconductor module 1E according to the third embodiment.
- the semiconductor module 1E has a configuration in which the semiconductor chip 20b in the semiconductor module 1 (see FIG. 1) exemplified in the first embodiment is changed to a high heat resistant chip 25b having high heat resistance as compared to the semiconductor chip 10a.
- the semiconductor chip 10a is also referred to as a low heat resistant chip 10a in this example.
- the plate-like insulating members 30ab and the like exemplified in the first embodiment are divided into one for the low heat resistant chip 10a and one for the high heat resistant chip 25b.
- the other configuration of the semiconductor module 1E is basically the same as that of the semiconductor module 1 described above.
- the plate-like insulating member 30a for the low heat resistant chip 10a has the main surfaces 31a and 32a which are in the relation of front and back.
- the main surface 31a is also referred to as the upper surface 31a
- the main surface 32a is also referred to as the lower surface 32a in accordance with the illustration of FIG.
- the case where the main surfaces 31a and 32a are flat and parallel to each other is exemplified.
- the thickness of the plate-like insulating member 30a is uniform over the entire member.
- the metal layer 40a is bonded to the upper surface 31a of the plate-like insulating member 30a, and the metal layer 40a is bonded to the lower surface 12 of the low heat resistant chip 10a by the bonding member 72a. Further, the metal layer 50a is bonded to the lower surface 32a of the plate-like insulating member 30a, and the metal layer 50a is bonded to the upper surface 61 of the heat sink 60 by the bonding member 74a.
- the plate-like insulating member 35b for the high heat resistant chip 25b has the main surfaces 36b and 37b which are in the relation of front and back.
- the main surface 36b is also referred to as the upper surface 36b and the main surface 37b is also referred to as the lower surface 37b in accordance with the illustration of FIG.
- the case where the main surfaces 36 b and 37 b are flat and parallel to each other is exemplified.
- the thickness of the plate-like insulating member 35 b is uniform over the entire member.
- the metal layer 40b is bonded to the upper surface 36b of the plate-like insulating member 35b, and the metal layer 40b is bonded to the lower surface 22 of the high heat resistant chip 25b by the bonding member 72b.
- the metal layer 50b is bonded to the lower surface 37a of the plate-like insulating member 35b, and the metal layer 50b is bonded to the upper surface 61 of the heat sink 60 by the bonding member 74b.
- the laminate of the plate-like insulating member 30a and the metal layers 40a and 50a and the laminate of the plate-like insulating member 35b and the metal layers 40b and 50b may be referred to as an insulating substrate.
- the plate-like insulating member 30a extends between the low heat-resistant chip 10a and the heat sink 60, and the plate-like insulating member between the high heat-resistant chip 25b and the heat sink 60
- the plate-like insulating member 30c extends between the low power part 90c and the heat sink 60.
- the thickness tc of the portion 33c facing the low power portion 90c in the plate-like insulating member 30c is smaller than the thickness ta of the portion 33a facing the low heat resistant chip 10a in the plate-like insulating member 30a. Large (tc> ta).
- the thickness tb of the portion 38b of the plate-like insulating member 35b facing the high heat resistant chip 25b is smaller than the thickness ta of the portion 33a of the plate like insulating member 30a facing the low heat resistant chip 10a. Large (tb> ta).
- tb tc in the example of FIG. 6, the present invention is not limited to this example.
- the semiconductor module 1E since the relationship between the low heat resistant chip 10a, the low power portion 90c, the plate-like insulating members 30a and 30c, and the heat sink 60 is the same as that of the first embodiment, the semiconductor module 1E is the first embodiment. It produces the same effect as
- the plate-like insulating member 35b for the high heat-resistant chip 25b is thicker than the plate-like insulating member 30a for the low heat-resistant chip 10a, the high heat-resistant chip 25b and the heat sink 60 via the plate-like insulating member 35b.
- the capacitive coupling between them can be reduced as compared with the capacitive coupling between the low heat resistant chip 20 a and the heat sink 60 through the plate-like insulating member 30 a. Therefore, the insulation between the high heat resistant chip 25 b and the low power portion 90 c and the insulation between the high heat resistant chip 25 b and the low heat resistant chip 10 a can be secured.
- the thermal resistance is increased by the thick plate-like insulating member 35b, since the high heat resistant chip 25b can operate at a higher temperature than the low heat resistant chip 10a, the normal operation of the high heat resistant chip 25b It can be secured.
- FIG. 7 illustrates a cross-sectional view of a semiconductor module 1F according to the fourth embodiment.
- the semiconductor module 1F has a configuration in which the plate-like insulating members 30a, 35b and 30c in the semiconductor module 1E (see FIG. 6) exemplified in the third embodiment are changed to plate-like insulating members 35abc.
- the other configuration of the semiconductor module 1F is basically the same as that of the semiconductor module 1E.
- the plate-like insulating member 35abc roughly corresponds to a member obtained by integrating the plate-like insulating members 30a, 35b and 30c (see FIG. 6) exemplified in the third embodiment. That is, the plate-like insulating member 35abc extends between the low heat resistant chip 10a and the heat sink 60, and also extends between the low power portion 90c and the heat sink 60, and further the high heat resistant chip 25b and the heat sink It also extends between 60 and.
- the plate-like insulating member 35abc has main surfaces 36abc and 37abc which are in a relation of front and back.
- the main surface 36abc is also referred to as the upper surface 36abc
- the main surface 37abc is also referred to as the lower surface 37abc in accordance with the illustration of FIG. 7.
- the thickness tc of the portion 33c of the plate insulating member 35ab facing the low power portion 90c is larger than the thickness ta of the portion 33a of the plate insulating member 35ab facing the low heat resistant chip 10a (see FIG. tc> ta).
- the thickness tb of the portion 38b of the plate-like insulating member 35ab facing the high heat resistant chip 25b is smaller than the thickness ta of the portion 33a of the plate-like insulating member 35ab facing the low heat resistant chip 10a. Large (tb> ta).
- tb tc in the example of FIG. 7, the present invention is not limited to this example.
- the area facing the low heat resistance chip 10a is lower than the area facing the low power portion 90c and the area facing the high heat resistance chip 25b.
- both regions are flat.
- the lower surface 37abc of the plate-like insulating member 35abc is flat in the example of FIG.
- Such a shape of the upper surface 36abc and the lower surface 37abc forms different thicknesses in the common plate-like insulating member 35abc.
- Such a difference in thickness can be formed, for example, in the same manner as the plate-like insulating member 30abc (see FIG. 3) exemplified in the second embodiment.
- the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the low power part 90c, the plate-like insulating member 35abc, and the heat sink 60 is the same as that of the third embodiment. The same effect as in the third embodiment is achieved.
- FIG. 8 illustrates a cross-sectional view of a semiconductor module 1G according to the fifth embodiment.
- the semiconductor module 1G has a configuration in which the plate-like insulating members 30a and 30c in the semiconductor module 1E (see FIG. 6) exemplified in the third embodiment are changed to a plate-like insulating member 30ac.
- the other configuration of the semiconductor module 1G is basically the same as that of the semiconductor module 1E.
- the plate-like insulating member 30ac roughly corresponds to a member in which the plate-like insulating members 30a and 30c (see FIG. 6) illustrated in the third embodiment are integrated. That is, the plate-like insulating member 30 ac extends between the low heat resistant chip 10 a and the heat sink 60 and also between the low power portion 90 c and the heat sink 60.
- the plate-like insulating member 30ac has main surfaces 31ac and 32ac which are in the relation of front and back.
- the main surface 31ac is also referred to as an upper surface 31ac
- the main surface 32ac is also referred to as a lower surface 32ac in accordance with the illustration of FIG.
- the thickness tc of the portion 33c of the plate insulating member 30ac facing the low power portion 90c is larger than the thickness ta of the portion 33a of the plate insulating member 30ac facing the low heat resistant chip 10a (see FIG. tc> ta).
- the region facing the low heat resistance chip 10a is located closer to the lower surface 32ac than the region facing the low power portion 90c. In the example of FIG. 8, all the regions are flat.
- the lower surface 32ac of the plate-like insulating member 30ac is flat in the example of FIG.
- Such a shape of the upper surface 31 ac and the lower surface 32 ac forms different thicknesses in the common plate-like insulating member 30 ac.
- Such a difference in thickness can be formed, for example, in the same manner as the plate-like insulating member 30abc (see FIG. 3) exemplified in the second embodiment.
- the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the low power portion 90c, the plate-like insulating members 30ac and 35b, and the heat sink 60 is the same as that of the third embodiment.
- 1G has the same effect as that of the third embodiment.
- FIG. 9 illustrates a cross-sectional view of a semiconductor module 1H according to the sixth embodiment.
- the semiconductor module 1H has a configuration in which the plate-like insulating members 30a and 35b are changed to a plate-like insulating member 35ab in the semiconductor module 1E (see FIG. 6) exemplified in the third embodiment.
- the other configuration of the semiconductor module 1H is basically the same as that of the semiconductor module 1E.
- the plate-like insulating member 35ab roughly corresponds to a member obtained by integrating the plate-like insulating members 30a and 35b (see FIG. 6) exemplified in the third embodiment. That is, the plate-like insulating member 35 ab extends between the low heat resistant chip 10 a and the heat sink 60 and also between the high heat resistant chip 25 b and the heat sink 60.
- the plate-like insulating member 35ab has main surfaces 36ab and 37ab which are in the relation of front and back.
- the main surface 36ab is also referred to as an upper surface 36ab
- the main surface 37ab is also referred to as a lower surface 37ab in accordance with the illustration of FIG.
- the thickness tb of the portion 38b of the plate insulating member 35ab facing the high heat resistant chip 25b is larger than the thickness ta of the portion 33a of the plate insulating member 35ab facing the low heat resistant chip 10a. (Tb> ta).
- the area facing the low heat resistant chip 10a is located closer to the lower surface 37ab than the area facing the high heat resistant chip 25b. In the example of FIG. 9, both regions are flat.
- the lower surface 37ab of the plate-like insulating member 35ab is flat in the example of FIG.
- the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the low power portion 90c, the plate-like insulating members 35ab and 30c, and the heat sink 60 is the same as that of the third embodiment. 1H exhibits the same effect as that of the third embodiment.
- FIG. 10 illustrates a cross-sectional view of a semiconductor module 1I according to the seventh embodiment.
- the semiconductor module 1I the low power portion 90c, the plate-like insulating member 30c, the metal layer 50c, the joining member 74c, and the connecting members 84 and 86 are omitted from the semiconductor module 1E (see FIG. 6) illustrated in the third embodiment. It has a configuration.
- the other configuration of the semiconductor module 1I is basically the same as that of the semiconductor module 1E.
- the configuration of the semiconductor module 1I omits the low power portion 90c, the metal layer 50c, the joining member 74c and the connecting members 84 and 86, It is also possible to think of a configuration in which the thick portion 33c for the low power portion 90c in the plate-like insulating member 30ac is omitted.
- the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the plate-like insulating members 30a and 35b, and the heat sink 60 is the same as that of the third embodiment. It produces the same effect as 3).
- FIG. 11 illustrates a cross-sectional view of a semiconductor module 1J according to the eighth embodiment.
- the semiconductor module 1J the low power portion 90c, the plate-like insulating member 30c, the metal layer 50c, the bonding member 74c, and the connecting members 84 and 86 are omitted from the semiconductor module 1H (see FIG. 9) illustrated in the sixth embodiment. It has a configuration.
- the other configuration of the semiconductor module 1J is basically the same as that of the semiconductor module 1H.
- the configuration of the semiconductor module 1J is such that the low power portion 90c, the metal layer 50c, the bonding member 74c and the connecting members 84 and 86 are omitted. It is also possible to think of a configuration in which the thick portion 33c for the low power portion 90c in the plate-like insulating member 35abc is omitted.
- the semiconductor module 1J since the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the plate-like insulating member 35ab, and the heat sink 60 is the same as that of the third embodiment, the semiconductor module 1J is different from the third embodiment. It plays the same effect.
- Embodiments 1 to 8 The present invention can freely combine each embodiment within the scope of the invention, and can suitably modify or omit each embodiment.
- 1, 1B to 1J semiconductor module 10a, 20b power semiconductor chip, 25b high heat resistant chip, 30ab, 30c, 30abc, 30a, 35b, 35abc, 30ac, 35ab plate-like insulating member, 60 heat sink, 61 main surfaces (predetermined surface 90c low power part, 33ab, 33a part facing power semiconductor chip, 33c part facing low power part, 38b part facing high heat resistant chip, tab, tc, ta, tb thickness.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
図1に、実施の形態1に係るパワー半導体モジュール(以下、半導体モジュールとも称する)1の断面図を例示する。図1の例によれば、半導体モジュール1は、パワー半導体チップ(以下、半導体チップとも称する)10a,20bと、板状絶縁部材30ab,30cと、金属層40ab,50ab,40c,50cと、ヒートシンク60と、接合部材72a,72b,74ab,74cと、接続部材82,84,86とを含んでいる。
図3に、実施の形態2に係る半導体モジュール1Bの断面図を例示する。半導体モジュール1Bは、実施の形態1で例示した半導体モジュール1(図1参照)において板状絶縁部材30ab,30cを板状絶縁部材30abcに変更した構成を有している。半導体モジュール1Bのその他の構成は基本的に上記半導体モジュール1と同様である。
図3に例示した半導体モジュール1Bは、板状絶縁部材30abcの上面31abcの端部に、突出部分34を有している。かかる突出部分34は、半導体チップ10a,20bに面する薄い部分33abを囲むように設けられている。なお、突出部分34の厚さは、図3の例ではtcに設定されているが、かかる例に限定されるものではない。
さて、炭化珪素(SiC)、窒化ガリウム(GaN)等のいわゆるワイドバンドギャップ材料で構成された半導体チップは、珪素(Si)で構成された半導体チップに比べて、高温動作が可能である。換言すれば、ワイドバンドギャップ半導体によれば、耐熱性の高いチップが提供される。実施の形態3では、耐熱性の異なる半導体チップが混在した半導体モジュールを説明する。以下では、耐熱性がより高い方の半導体チップを高耐熱性チップとも称し、耐熱性がより低い方の半導体チップを便宜上、低耐熱性チップとも称する。
図7に、実施の形態4に係る半導体モジュール1Fの断面図を例示する。半導体モジュール1Fは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,35b,30cを板状絶縁部材35abcに変更した構成を有している。半導体モジュール1Fのその他の構成は基本的に上記半導体モジュール1Eと同様である。
図8に、実施の形態5に係る半導体モジュール1Gの断面図を例示する。半導体モジュール1Gは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,30cを板状絶縁部材30acに変更した構成を有している。半導体モジュール1Gのその他の構成は基本的に上記半導体モジュール1Eと同様である。
図9に、実施の形態6に係る半導体モジュール1Hの断面図を例示する。半導体モジュール1Hは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,35bを板状絶縁部材35abに変更した構成を有している。半導体モジュール1Hのその他の構成は基本的に上記半導体モジュール1Eと同様である。
図10に、実施の形態7に係る半導体モジュール1Iの断面図を例示する。半導体モジュール1Iは、実施の形態3で例示した半導体モジュール1E(図6参照)から、低電力部90cと板状絶縁部材30cと金属層50cと接合部材74cと接続部材84,86とを省略した構成を有している。半導体モジュール1Iのその他の構成は基本的に上記半導体モジュール1Eと同様である。
図11に、実施の形態8に係る半導体モジュール1Jの断面図を例示する。半導体モジュール1Jは、実施の形態6で例示した半導体モジュール1H(図9参照)から、低電力部90cと板状絶縁部材30cと金属層50cと接合部材74cと接続部材84,86とを省略した構成を有している。半導体モジュール1Jのその他の構成は基本的に上記半導体モジュール1Hと同様である。
実施の形態1,2の変形例で例示した突出部分34(図3および図5参照)は、実施の形態3~8にも採用可能である。
本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。
Claims (8)
- 導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a,20b)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a,20b)に比べて消費電力が低い低電力部(90c)と、
前記パワー半導体チップ(10a,20b)と前記ヒートシンク(60)との間に延在した第1の板状絶縁部材(30ab,30a,35ab)と、
前記低電力部(90c)と前記ヒートシンク(60)との間に延在した第2の板状絶縁部材(30c)と
を備え、
前記第2の板状絶縁部材(30c)のうちで前記低電力部(90c)に面する部分(33c)は、前記第1の板状絶縁部材(30ab,30a,35ab)のうちで前記パワー半導体チップ(10a,20b)に面する部分(33ab,33a)に比べて厚い、半導体モジュール(1,1D,1E,1H)。 - 前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した第3の板状絶縁部材(35b)と
を更に備え、
前記第3の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記第1の板状絶縁部材(30a)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項1に記載の半導体モジュール(1E)。 - 前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)を更に備え、
前記第1の板状絶縁部材(35ab)は前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在しており、
前記第1の板状絶縁部材(35ab)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記第1の板状絶縁部材(35ab)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項1に記載の半導体モジュール(1H)。 - 導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a,20b)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a,20b)に比べて消費電力が低い低電力部(90c)と、
前記パワー半導体チップ(10a,20b)と前記ヒートシンク(60)との間に延在すると共に前記低電力部(90c)と前記ヒートシンク(60)との間にも延在した共通の板状絶縁部材(30abc,35abc,30ac)と
を備え、
前記共通の板状絶縁部材(30abc,35abc,30ac)のうちで前記低電力部(90c)に面する部分(33c)は、前記共通の板状絶縁部材(30abc,35abc,30ac)のうちで前記パワー半導体チップ(10a,20b)に面する部分(33ab,33a)に比べて厚い、半導体モジュール(1B,1C,1F,1G)。 - 前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)を更に備え、
前記共通の板状絶縁部材(35abc)は前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在しており、
前記共通の板状絶縁部材(35abc)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(35abc)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項4に記載の半導体モジュール(1F)。 - 前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した別の板状絶縁部材(35b)と
を更に備え、
前記別の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(30ac)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項4に記載の半導体モジュール(1G)。 - 導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記パワー半導体チップ(10a)と前記ヒートシンク(60)との間に延在した板状絶縁部材(30a,30ac)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した別の板状絶縁部材(35b)と
を備え、
前記別の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記板状絶縁部材(30a,30ac)のうちで前記パワー半導体チップ(10a)に面する部分(33a)に比べて厚い、半導体モジュール(1E,1G,1I)。 - 導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記パワー半導体チップ(10a)と前記ヒートシンク(60)との間に延在すると共に前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在した共通の板状絶縁部材(35abc,35ab)と
を備え、
前記共通の板状絶縁部材(35abc,35ab)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(35abc,35ab)のうちで前記パワー半導体チップ(10a)に面する部分(33a)に比べて厚い、半導体モジュール(1F,1H,1J)。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/371,854 US9443784B2 (en) | 2012-03-09 | 2012-03-09 | Semiconductor module including plate-shaped insulating members having different thickness |
DE112012006007.5T DE112012006007T5 (de) | 2012-03-09 | 2012-03-09 | Halbleitermodul |
PCT/JP2012/056078 WO2013132644A1 (ja) | 2012-03-09 | 2012-03-09 | 半導体モジュール |
CN201280071262.6A CN104160502A (zh) | 2012-03-09 | 2012-03-09 | 半导体模块 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2012/056078 WO2013132644A1 (ja) | 2012-03-09 | 2012-03-09 | 半導体モジュール |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013132644A1 true WO2013132644A1 (ja) | 2013-09-12 |
Family
ID=49116157
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/056078 WO2013132644A1 (ja) | 2012-03-09 | 2012-03-09 | 半導体モジュール |
Country Status (4)
Country | Link |
---|---|
US (1) | US9443784B2 (ja) |
CN (1) | CN104160502A (ja) |
DE (1) | DE112012006007T5 (ja) |
WO (1) | WO2013132644A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015115342A (ja) * | 2013-12-09 | 2015-06-22 | 三菱電機株式会社 | 電子部品実装装置及びそれを備える半導体装置 |
JP2018186302A (ja) * | 2018-08-20 | 2018-11-22 | 三菱電機株式会社 | 半導体装置およびそれを備える半導体モジュール |
US10361136B2 (en) | 2015-09-29 | 2019-07-23 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor module provided with same |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6196195B2 (ja) * | 2014-08-19 | 2017-09-13 | 株式会社東芝 | 半導体モジュール |
JP2021002644A (ja) * | 2019-06-21 | 2021-01-07 | 株式会社村田製作所 | 半導体装置及びその製造方法 |
WO2021154957A1 (en) * | 2020-01-28 | 2021-08-05 | Littelfuse, Inc. | Semiconductor chip package and method of assembly |
DE102020106385A1 (de) * | 2020-03-09 | 2021-09-09 | Danfoss Silicon Power Gmbh | Leistungsmodul |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61136547U (ja) * | 1985-02-12 | 1986-08-25 | ||
JPH0226058A (ja) * | 1988-07-15 | 1990-01-29 | Hitachi Ltd | 混成集積回路用ヒートシンク |
JPH05166963A (ja) * | 1991-12-19 | 1993-07-02 | Fuji Electric Co Ltd | 半導体装置 |
JP2005332918A (ja) * | 2004-05-19 | 2005-12-02 | Denso Corp | 電子装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03160751A (ja) | 1989-11-17 | 1991-07-10 | Mitsubishi Electric Corp | 半導体装置 |
JP2848068B2 (ja) | 1991-12-10 | 1999-01-20 | 富士電機株式会社 | 半導体装置 |
JP2656416B2 (ja) | 1991-12-16 | 1997-09-24 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法、並びに半導体装置に用いられる複合基板および複合基板の製造方法 |
JPH08298299A (ja) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | 半導体装置 |
JP3516789B2 (ja) | 1995-11-15 | 2004-04-05 | 三菱電機株式会社 | 半導体パワーモジュール |
JPH1117081A (ja) * | 1997-06-19 | 1999-01-22 | Sansha Electric Mfg Co Ltd | 電力用半導体モジュール |
DE19735531A1 (de) * | 1997-08-16 | 1999-02-18 | Abb Research Ltd | Leistungshalbleitermodul mit in Submodulen integrierten Kühlern |
JPH11233712A (ja) | 1998-02-12 | 1999-08-27 | Hitachi Ltd | 半導体装置及びその製法とそれを使った電気機器 |
JP2000349209A (ja) * | 1999-06-09 | 2000-12-15 | Mitsubishi Electric Corp | パワー半導体モジュール |
JP4096741B2 (ja) | 2003-01-16 | 2008-06-04 | 松下電器産業株式会社 | 半導体装置 |
JP2006196853A (ja) | 2004-12-13 | 2006-07-27 | Daikin Ind Ltd | ヒートポンプ装置 |
JP5271487B2 (ja) | 2006-08-31 | 2013-08-21 | ダイキン工業株式会社 | 電力変換装置 |
JP5206102B2 (ja) | 2008-05-08 | 2013-06-12 | トヨタ自動車株式会社 | 半導体装置 |
JP5381561B2 (ja) * | 2008-11-28 | 2014-01-08 | 富士電機株式会社 | 半導体冷却装置 |
US8202765B2 (en) * | 2009-01-22 | 2012-06-19 | International Business Machines Corporation | Achieving mechanical and thermal stability in a multi-chip package |
JP4988784B2 (ja) | 2009-03-30 | 2012-08-01 | 株式会社日立製作所 | パワー半導体装置 |
JP5182274B2 (ja) * | 2009-11-17 | 2013-04-17 | 三菱電機株式会社 | パワー半導体装置 |
-
2012
- 2012-03-09 US US14/371,854 patent/US9443784B2/en not_active Expired - Fee Related
- 2012-03-09 WO PCT/JP2012/056078 patent/WO2013132644A1/ja active Application Filing
- 2012-03-09 DE DE112012006007.5T patent/DE112012006007T5/de not_active Withdrawn
- 2012-03-09 CN CN201280071262.6A patent/CN104160502A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61136547U (ja) * | 1985-02-12 | 1986-08-25 | ||
JPH0226058A (ja) * | 1988-07-15 | 1990-01-29 | Hitachi Ltd | 混成集積回路用ヒートシンク |
JPH05166963A (ja) * | 1991-12-19 | 1993-07-02 | Fuji Electric Co Ltd | 半導体装置 |
JP2005332918A (ja) * | 2004-05-19 | 2005-12-02 | Denso Corp | 電子装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015115342A (ja) * | 2013-12-09 | 2015-06-22 | 三菱電機株式会社 | 電子部品実装装置及びそれを備える半導体装置 |
US9723718B2 (en) | 2013-12-09 | 2017-08-01 | Mitsubishi Electric Corporation | Electronic component mounting device and semiconductor device including the same |
US10361136B2 (en) | 2015-09-29 | 2019-07-23 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor module provided with same |
JP2018186302A (ja) * | 2018-08-20 | 2018-11-22 | 三菱電機株式会社 | 半導体装置およびそれを備える半導体モジュール |
Also Published As
Publication number | Publication date |
---|---|
CN104160502A (zh) | 2014-11-19 |
US9443784B2 (en) | 2016-09-13 |
US20150084179A1 (en) | 2015-03-26 |
DE112012006007T5 (de) | 2014-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2013132644A1 (ja) | 半導体モジュール | |
US9171773B2 (en) | Semiconductor device | |
US9627356B2 (en) | Semiconductor module, semiconductor module arrangement and method for operating a semiconductor module | |
US20120175755A1 (en) | Semiconductor device including a heat spreader | |
JP2008166461A (ja) | 双方向スイッチモジュール | |
US9385107B2 (en) | Multichip device including a substrate | |
JP6604926B2 (ja) | 半導体モジュール | |
US20100308457A1 (en) | Semiconductor apparatus and manufacturing method of the same | |
WO2014103133A1 (ja) | 半導体装置 | |
WO2020241238A1 (ja) | 半導体装置 | |
WO2015005181A1 (ja) | 電力変換部品 | |
WO2020121680A1 (ja) | 半導体装置 | |
JP2019067951A (ja) | 半導体装置 | |
CN104851843A (zh) | 电力用半导体装置 | |
US10727150B2 (en) | Semiconductor module and power converter | |
WO2018198747A1 (ja) | 半導体装置 | |
JP4816214B2 (ja) | 半導体装置及びその製造方法 | |
JP2004221381A (ja) | 半導体装置 | |
US10566295B2 (en) | Semiconductor device | |
JP2015173299A (ja) | 半導体モジュール | |
JP2019140157A (ja) | 半導体装置 | |
JPWO2013132644A1 (ja) | 半導体モジュール | |
WO2020241239A1 (ja) | 半導体装置 | |
CN111354709A (zh) | 半导体装置及其制造方法 | |
CN110943062A (zh) | 半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12870899 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2014503390 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14371854 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1120120060075 Country of ref document: DE Ref document number: 112012006007 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12870899 Country of ref document: EP Kind code of ref document: A1 |