JP2014517531A5 - - Google Patents

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Publication number
JP2014517531A5
JP2014517531A5 JP2014513727A JP2014513727A JP2014517531A5 JP 2014517531 A5 JP2014517531 A5 JP 2014517531A5 JP 2014513727 A JP2014513727 A JP 2014513727A JP 2014513727 A JP2014513727 A JP 2014513727A JP 2014517531 A5 JP2014517531 A5 JP 2014517531A5
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JP
Japan
Prior art keywords
tsv
die
bottom side
protruding
bonding
Prior art date
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JP2014513727A
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English (en)
Japanese (ja)
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JP2014517531A (ja
JP6038902B2 (ja
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Priority claimed from US13/150,899 external-priority patent/US8623763B2/en
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Publication of JP2014517531A publication Critical patent/JP2014517531A/ja
Publication of JP2014517531A5 publication Critical patent/JP2014517531A5/ja
Application granted granted Critical
Publication of JP6038902B2 publication Critical patent/JP6038902B2/ja
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JP2014513727A 2011-06-01 2012-06-01 熱圧着ボンディングの間tsvティップを保護するための保護層 Active JP6038902B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/150,899 2011-06-01
US13/150,899 US8623763B2 (en) 2011-06-01 2011-06-01 Protective layer for protecting TSV tips during thermo-compressive bonding
PCT/US2012/040388 WO2012167027A2 (en) 2011-06-01 2012-06-01 Protective layer for protecting tsv tips during thermo-compressive bonding

Publications (3)

Publication Number Publication Date
JP2014517531A JP2014517531A (ja) 2014-07-17
JP2014517531A5 true JP2014517531A5 (enExample) 2015-07-16
JP6038902B2 JP6038902B2 (ja) 2016-12-07

Family

ID=47260364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014513727A Active JP6038902B2 (ja) 2011-06-01 2012-06-01 熱圧着ボンディングの間tsvティップを保護するための保護層

Country Status (5)

Country Link
US (2) US8623763B2 (enExample)
EP (1) EP2783393A4 (enExample)
JP (1) JP6038902B2 (enExample)
CN (1) CN103718286A (enExample)
WO (1) WO2012167027A2 (enExample)

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CN104810319A (zh) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 晶圆键合的方法
EP2908337B1 (en) * 2014-02-12 2025-11-12 ams AG Semiconductor device with a thermally stable bump contact on a TSV and method of producing such a semiconductor device
WO2016007176A1 (en) 2014-07-11 2016-01-14 Intel Corporation Scalable package architecture and associated techniques and configurations
JP2016039512A (ja) * 2014-08-08 2016-03-22 キヤノン株式会社 電極が貫通配線と繋がったデバイス、及びその製造方法
CN104502903B (zh) * 2014-11-28 2017-12-29 成都嘉纳海威科技有限责任公司 一种基于tsv转接板的多波束接收sip系统
WO2016154526A1 (en) * 2015-03-26 2016-09-29 Board Of Regents, The University Of Texas System Capped through-silicon-vias for 3d integrated circuits
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US11469194B2 (en) * 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems
EP4268274A4 (en) 2020-12-28 2024-10-30 Adeia Semiconductor Bonding Technologies Inc. STRUCTURES COMPRISING THROUGH-THROUGH-SUBSTRATE VIA HOLES AND METHODS OF FORMING SAME
KR20230125309A (ko) 2020-12-28 2023-08-29 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법
US20250218903A1 (en) * 2023-12-28 2025-07-03 Adeia Semiconductor Bonding Technologies Inc. Via reveal processing and structures

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