JP2014517531A5 - - Google Patents
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- Publication number
- JP2014517531A5 JP2014517531A5 JP2014513727A JP2014513727A JP2014517531A5 JP 2014517531 A5 JP2014517531 A5 JP 2014517531A5 JP 2014513727 A JP2014513727 A JP 2014513727A JP 2014513727 A JP2014513727 A JP 2014513727A JP 2014517531 A5 JP2014517531 A5 JP 2014517531A5
- Authority
- JP
- Japan
- Prior art keywords
- tsv
- die
- bottom side
- protruding
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/150,899 | 2011-06-01 | ||
| US13/150,899 US8623763B2 (en) | 2011-06-01 | 2011-06-01 | Protective layer for protecting TSV tips during thermo-compressive bonding |
| PCT/US2012/040388 WO2012167027A2 (en) | 2011-06-01 | 2012-06-01 | Protective layer for protecting tsv tips during thermo-compressive bonding |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014517531A JP2014517531A (ja) | 2014-07-17 |
| JP2014517531A5 true JP2014517531A5 (enExample) | 2015-07-16 |
| JP6038902B2 JP6038902B2 (ja) | 2016-12-07 |
Family
ID=47260364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014513727A Active JP6038902B2 (ja) | 2011-06-01 | 2012-06-01 | 熱圧着ボンディングの間tsvティップを保護するための保護層 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8623763B2 (enExample) |
| EP (1) | EP2783393A4 (enExample) |
| JP (1) | JP6038902B2 (enExample) |
| CN (1) | CN103718286A (enExample) |
| WO (1) | WO2012167027A2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8970043B2 (en) | 2011-02-01 | 2015-03-03 | Maxim Integrated Products, Inc. | Bonded stacked wafers and methods of electroplating bonded stacked wafers |
| KR101916225B1 (ko) * | 2012-04-09 | 2018-11-07 | 삼성전자 주식회사 | Tsv를 구비한 반도체 칩 및 그 반도체 칩 제조방법 |
| US8907494B2 (en) * | 2013-03-14 | 2014-12-09 | International Business Machines Corporation | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures |
| CN104810319A (zh) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 晶圆键合的方法 |
| EP2908337B1 (en) * | 2014-02-12 | 2025-11-12 | ams AG | Semiconductor device with a thermally stable bump contact on a TSV and method of producing such a semiconductor device |
| WO2016007176A1 (en) | 2014-07-11 | 2016-01-14 | Intel Corporation | Scalable package architecture and associated techniques and configurations |
| JP2016039512A (ja) * | 2014-08-08 | 2016-03-22 | キヤノン株式会社 | 電極が貫通配線と繋がったデバイス、及びその製造方法 |
| CN104502903B (zh) * | 2014-11-28 | 2017-12-29 | 成都嘉纳海威科技有限责任公司 | 一种基于tsv转接板的多波束接收sip系统 |
| WO2016154526A1 (en) * | 2015-03-26 | 2016-09-29 | Board Of Regents, The University Of Texas System | Capped through-silicon-vias for 3d integrated circuits |
| KR102649471B1 (ko) | 2016-09-05 | 2024-03-21 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
| US11469194B2 (en) * | 2018-08-08 | 2022-10-11 | Stmicroelectronics S.R.L. | Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer |
| US11152333B2 (en) * | 2018-10-19 | 2021-10-19 | Micron Technology, Inc. | Semiconductor device packages with enhanced heat management and related systems |
| EP4268274A4 (en) | 2020-12-28 | 2024-10-30 | Adeia Semiconductor Bonding Technologies Inc. | STRUCTURES COMPRISING THROUGH-THROUGH-SUBSTRATE VIA HOLES AND METHODS OF FORMING SAME |
| KR20230125309A (ko) | 2020-12-28 | 2023-08-29 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법 |
| US20250218903A1 (en) * | 2023-12-28 | 2025-07-03 | Adeia Semiconductor Bonding Technologies Inc. | Via reveal processing and structures |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990063586A (ko) * | 1996-07-12 | 1999-07-26 | 아끼구사 나오유끼 | 반도체 장치의 제조 방법 및 반도체 장치 제조용 금형 및 반도체 장치 및 그 실장방법 |
| JP4151164B2 (ja) * | 1999-03-19 | 2008-09-17 | 株式会社デンソー | 半導体装置の製造方法 |
| US6734532B2 (en) * | 2001-12-06 | 2004-05-11 | Texas Instruments Incorporated | Back side coating of semiconductor wafers |
| US6713366B2 (en) * | 2002-06-12 | 2004-03-30 | Intel Corporation | Method of thinning a wafer utilizing a laminated reinforcing layer over the device side |
| US6864165B1 (en) * | 2003-09-15 | 2005-03-08 | International Business Machines Corporation | Method of fabricating integrated electronic chip with an interconnect device |
| TWI309456B (en) * | 2004-04-27 | 2009-05-01 | Advanced Semiconductor Eng | Chip package structure and process for fabricating the same |
| EP1742255B1 (en) * | 2004-04-28 | 2012-10-31 | Lintec Corporation | Sheet peeling apparatus and peeling method |
| JP4369348B2 (ja) * | 2004-11-08 | 2009-11-18 | 新光電気工業株式会社 | 基板及びその製造方法 |
| CN101356637B (zh) * | 2005-11-08 | 2012-06-06 | Nxp股份有限公司 | 使用临时帽层产生受到覆盖的穿透衬底的通道 |
| JP2007317822A (ja) * | 2006-05-25 | 2007-12-06 | Sony Corp | 基板処理方法及び半導体装置の製造方法 |
| KR20090075883A (ko) * | 2006-10-31 | 2009-07-09 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | 알루미늄 단자 금속층이 없는 금속화층 스택 |
| KR100871382B1 (ko) * | 2007-06-26 | 2008-12-02 | 주식회사 하이닉스반도체 | 관통 실리콘 비아 스택 패키지 및 그의 제조 방법 |
| JP5159273B2 (ja) * | 2007-11-28 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 電子装置の製造方法 |
| US7759212B2 (en) * | 2007-12-26 | 2010-07-20 | Stats Chippac, Ltd. | System-in-package having integrated passive devices and method therefor |
| US8178976B2 (en) * | 2008-05-12 | 2012-05-15 | Texas Instruments Incorporated | IC device having low resistance TSV comprising ground connection |
| US8334170B2 (en) * | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
| KR20100021856A (ko) | 2008-08-18 | 2010-02-26 | 삼성전자주식회사 | 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치 |
| US7687311B1 (en) * | 2008-11-13 | 2010-03-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing stackable dies |
| US8097964B2 (en) | 2008-12-29 | 2012-01-17 | Texas Instruments Incorporated | IC having TSV arrays with reduced TSV induced stress |
| TWI380421B (en) | 2009-03-13 | 2012-12-21 | Advanced Semiconductor Eng | Method for making silicon wafer having through via |
| JP5563785B2 (ja) * | 2009-05-14 | 2014-07-30 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法 |
| US20100327465A1 (en) * | 2009-06-25 | 2010-12-30 | Advanced Semiconductor Engineering, Inc. | Package process and package structure |
| US8313982B2 (en) * | 2010-09-20 | 2012-11-20 | Texas Instruments Incorporated | Stacked die assemblies including TSV die |
| TWI429055B (zh) * | 2010-10-07 | 2014-03-01 | 日月光半導體製造股份有限公司 | 堆疊式封裝結構及其製造方法 |
| CN102054787B (zh) | 2010-10-21 | 2013-08-14 | 日月光半导体制造股份有限公司 | 堆栈式封装结构及其制造方法 |
| US8298944B1 (en) * | 2011-06-01 | 2012-10-30 | Texas Instruments Incorporated | Warpage control for die with protruding TSV tips during thermo-compressive bonding |
-
2011
- 2011-06-01 US US13/150,899 patent/US8623763B2/en active Active
-
2012
- 2012-06-01 EP EP12792149.2A patent/EP2783393A4/en not_active Withdrawn
- 2012-06-01 CN CN201280037713.4A patent/CN103718286A/zh active Pending
- 2012-06-01 WO PCT/US2012/040388 patent/WO2012167027A2/en not_active Ceased
- 2012-06-01 JP JP2014513727A patent/JP6038902B2/ja active Active
-
2013
- 2013-05-15 US US13/894,536 patent/US8723330B2/en active Active
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