JP2014199921A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2014199921A JP2014199921A JP2014043410A JP2014043410A JP2014199921A JP 2014199921 A JP2014199921 A JP 2014199921A JP 2014043410 A JP2014043410 A JP 2014043410A JP 2014043410 A JP2014043410 A JP 2014043410A JP 2014199921 A JP2014199921 A JP 2014199921A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
Description
本実施の形態では、本発明の一態様の半導体装置であるトランジスタについて図面を用いて説明する。
本実施の形態では、実施の形態1で説明したトランジスタの作製方法とは異なる作製方法について図を用いて説明する。
本実施の形態では、実施の形態1で説明したトランジスタとは異なる構造のトランジスタについて説明する。
本実施の形態では、本発明の一態様であるトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を、図面を用いて説明する。
本実施の形態では、本発明の一態様であるトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置について、実施の形態4に示した構成と異なる半導体装置の説明を行う。
本実施の形態では、先の実施の形態で説明したトランジスタを用いることのできる電子機器の例について説明する。
102 下地絶縁膜
103 酸化物半導体膜
104 酸化物半導体膜
105 ハードマスク
106 ハードマスク
106a ハードマスク
106b ハードマスク
107 ハードマスク
108 ハードマスク
108a ハードマスク
108b ハードマスク
110a ソース電極
110b ドレイン電極
112 ゲート絶縁膜
114 ゲート電極
116 絶縁膜
120 低抵抗領域
120a 低抵抗領域
120b 低抵抗領域
121a 低抵抗領域
121b 低抵抗領域
122 レジストマスク
124 レジストマスク
130 酸素
150 トランジスタ
203 多層膜
203a 酸化物膜
203b 酸化物半導体膜
203c 酸化物膜
204 多層膜
204a 酸化物膜
204b 酸化物半導体膜
204c 酸化物膜
250 トランジスタ
260 トランジスタ
400 トランジスタ
402 トランジスタ
404 容量素子
406 素子分離絶縁層
410 基板
420 絶縁膜
550 メモリセル
551 メモリセルアレイ
551a メモリセルアレイ
551b メモリセルアレイ
553 周辺回路
554 容量素子
562 トランジスタ
700 マイクロコンピュータ
701 直流電源
702 バスライン
703 パワーゲートコントローラー
704 パワーゲート
705 CPU
706 揮発性記憶部
707 不揮発性記憶部
708 インターフェース
709 検出部
711 光センサ
712 アンプ
713 ADコンバータ
730 発光素子
801 半導体基板
803 素子分離領域
804 ゲート電極
805a 低抵抗領域
805b 低抵抗領域
806a 酸化物膜
806b 酸化物半導体膜
806c 酸化物膜
807 ゲート絶縁膜
809 ゲート電極
811a 不純物領域
811b 不純物領域
812 ゲート絶縁膜
815 絶縁膜
816a ソース電極
816b ドレイン電極
816c 電極
817 絶縁膜
818 酸化物絶縁膜
819a コンタクトプラグ
819b コンタクトプラグ
820 絶縁膜
821 絶縁膜
822 絶縁膜
823a 配線
823b 配線
825 絶縁膜
831 ハードマスク
832 ハードマスク
845 絶縁膜
849 配線
856 配線
860 半導体膜
870 トランジスタ
880 トランジスタ
890 光電変換素子
901 スイッチング素子
902 メモリセル
903 メモリセル群
919 ROMインターフェース
920 基板
921 ALU
922 ALUコントローラ
923 インストラクションデコーダ
924 インタラプトコントローラ
925 タイミングコントローラ
926 レジスタ
927 レジスタコントローラ
928 バスインターフェース
929 ROM
1000 表示装置
1001 筐体
1002 表示部
1003 スピーカー部
1004 CPU
1010 警報装置
1011 マイクロコンピュータ
1020 室内機
1021 筐体
1022 送風口
1023 CPU
1024 室外機
1030 電気冷凍冷蔵庫
1031 筐体
1032 冷蔵室用扉
1033 冷凍室用扉
1034 CPU
1040 電気自動車
1041 二次電池
1042 制御回路
1043 駆動装置
1044 処理装置
Claims (7)
- 絶縁表面上の酸化物半導体膜と、
前記酸化物半導体膜上の第1のハードマスクおよび第2のハードマスクと、
前記酸化物半導体膜および前記第1のハードマスク上のソース電極と、
前記酸化物半導体膜および前記第2のハードマスク上のドレイン電極と、
前記ソース電極および前記ドレイン電極上のゲート絶縁膜と、
前記ゲート絶縁膜と前記酸化物半導体膜と重畳するゲート電極と、を有し、
前記第1のハードマスクおよび前記第2のハードマスクは、導電性を有する膜であることを特徴とする半導体装置。 - 絶縁表面上の酸化物半導体膜と、
前記酸化物半導体膜上の第1のハードマスクおよび第2のハードマスクと、
前記酸化物半導体膜および前記第1のハードマスク上のソース電極と、
前記酸化物半導体膜および前記第2のハードマスク上のドレイン電極と、
前記ソース電極および前記ドレイン電極上のゲート絶縁膜と、
前記ゲート絶縁膜と前記酸化物半導体膜と重畳するゲート電極と、を有し、
前記第1のハードマスクおよび前記第2のハードマスクは、積層膜であり、
前記積層膜の前記酸化物半導体膜と接する膜は、導電性を有する膜であることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記酸化物半導体膜を挟む第1の酸化物膜および第2の酸化物膜を有し、
前記第1の酸化物膜および前記第2の酸化物膜は、前記酸化物半導体膜よりも伝導帯下端のエネルギーが0.05eV以上2eV以下の範囲で真空準位に近いことを特徴とする半導体装置。 - 請求項1乃至請求項3において、
前記酸化物半導体膜と前記ソース電極との間、および前記酸化物半導体膜と前記導電性を有する膜との間に設けられた第1の低抵抗領域と、
前記酸化物半導体膜と前記ドレイン電極との間、および前記酸化物半導体膜と前記導電性を有する膜との間に設けられた第2の低抵抗領域と、を有することを特徴とする半導体装置。 - 絶縁表面上に第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜上に第1のハードマスクを形成し、
前記第1のハードマスク上に第1のレジストを形成し、
露光を行い、第1のレジストマスクを形成し、
前記第1のレジストマスクをマスクとして、前記第1のハードマスクをエッチングして第2のハードマスクを形成し、
前記第1のレジストマスクを除去し、
前記第2のハードマスクをマスクとして、前記第1の酸化物半導体膜をエッチングして第2の酸化物半導体膜を形成し、
前記絶縁表面、前記第2の酸化物半導体膜および前記第2のハードマスク上にソース電極およびドレイン電極を形成し、
前記第2のハードマスク、前記ソース電極および前記ドレイン電極上に第2のレジストを形成し、
露光を行い、第2のレジストマスクを形成し、
前記第2のレジストマスクをマスクとして、前記第2のハードマスクをエッチングして一対の第3のハードマスクを形成し、
前記第2のレジストマスクを除去し、
前記第2の酸化物半導体膜、前記ソース電極、前記ドレイン電極および前記一対の第3のハードマスク上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に前記第2の酸化物半導体膜と重畳するゲート電極を形成することを特徴とする半導体装置の作製方法。 - 絶縁表面上に第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜上に第1のハードマスクを形成し、
前記第1のハードマスク上に第1のレジストを形成し、
露光を行い、第1のレジストマスクを形成し、
前記第1のレジストマスクをマスクとして、前記第1のハードマスクをエッチングして第2のハードマスクを形成し、
前記第1のレジストマスクを除去し、
前記第2のハードマスクをマスクとして、前記第1の酸化物半導体膜をエッチングして第2の酸化物半導体膜を形成し、
前記絶縁表面、前記第2の酸化物半導体膜および前記第2のハードマスク上に第2のレジストを形成し、
露光を行い、第2のレジストマスクを形成し、
前記第2のレジストマスクをマスクとして、前記第2のハードマスクをエッチングして一対の第3のハードマスクを形成し、
前記第2のレジストマスクを除去し、
前記絶縁表面、前記第2の酸化物半導体膜および前記一対の第3のハードマスク上にソース電極およびドレイン電極を形成し、
前記第2の酸化物半導体膜、前記ソース電極、前記ドレイン電極および前記一対の第3のハードマスク上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上に前記第2の酸化物半導体膜と重畳するゲート電極を形成することを特徴とする半導体装置の作製方法。 - 請求項5または請求項6において、
前記露光は、電子ビーム露光または液浸露光であることを特徴とする半導体装置の作製方法。
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JP7132404B2 (ja) | 2015-02-06 | 2022-09-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2016213457A (ja) * | 2015-05-04 | 2016-12-15 | 株式会社半導体エネルギー研究所 | 半導体装置、半導体装置の作製方法、および電子機器 |
US10797180B2 (en) | 2015-05-04 | 2020-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, method for manufacturing the same, and electronic device |
JP2017034243A (ja) * | 2015-07-30 | 2017-02-09 | 株式会社半導体エネルギー研究所 | 半導体装置及び電子機器 |
JP2017045989A (ja) * | 2015-08-26 | 2017-03-02 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
US9773919B2 (en) | 2015-08-26 | 2017-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9935203B2 (en) | 2015-08-26 | 2018-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2020053680A (ja) * | 2018-08-31 | 2020-04-02 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
JP7442997B2 (ja) | 2018-08-31 | 2024-03-05 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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JP2016028441A (ja) | 2016-02-25 |
TWI642190B (zh) | 2018-11-21 |
US20140264323A1 (en) | 2014-09-18 |
TW201444090A (zh) | 2014-11-16 |
US9437744B2 (en) | 2016-09-06 |
KR20140113354A (ko) | 2014-09-24 |
JP2018137475A (ja) | 2018-08-30 |
US20160359050A1 (en) | 2016-12-08 |
JP6503111B2 (ja) | 2019-04-17 |
US9991395B2 (en) | 2018-06-05 |
JP6329395B2 (ja) | 2018-05-23 |
KR102290247B1 (ko) | 2021-08-13 |
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