JP2014135465A - Cu配線の形成方法 - Google Patents
Cu配線の形成方法 Download PDFInfo
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- JP2014135465A JP2014135465A JP2013067196A JP2013067196A JP2014135465A JP 2014135465 A JP2014135465 A JP 2014135465A JP 2013067196 A JP2013067196 A JP 2013067196A JP 2013067196 A JP2013067196 A JP 2013067196A JP 2014135465 A JP2014135465 A JP 2014135465A
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- film
- forming
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- 239000000126 substance Substances 0.000 claims description 23
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- 239000011572 manganese Substances 0.000 description 95
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- 238000007747 plating Methods 0.000 description 7
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- HLDBBQREZCVBMA-UHFFFAOYSA-N hydroxy-tris[(2-methylpropan-2-yl)oxy]silane Chemical compound CC(C)(C)O[Si](O)(OC(C)(C)C)OC(C)(C)C HLDBBQREZCVBMA-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
- C23C14/354—Introduction of auxiliary energy into the plasma
- C23C14/358—Inductive energy
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- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
【解決手段】表面に所定パターンのトレンチ203が形成されたSi含有膜である層間絶縁膜202を有するウエハWに対し、トレンチ203を埋めるCu配線208を形成するCu配線の形成方法であり、少なくともトレンチ203の表面に、下地との反応で自己整合バリア膜となるMn膜204をCVDにより形成する工程と、Cu膜207をPVDにより形成してトレンチ203内にCu膜を埋め込む工程と、CMPにより全面を研磨してトレンチ203内にCu配線208を形成する工程とを有する。
【選択図】 図2
Description
まず、Cu配線の形成方法の一実施形態について図1のフローチャートおよび図2の工程断面図を参照して説明する。
Mn膜204は上述したようにCVD(Chemical Vapor Deposition)により成膜する。CVDの一種であるALD(Atomic Layer Deposition)で成膜してもよい。CVDによりMn膜を成膜する際の熱により、成膜の際の熱では不十分な場合には、その熱にその後に与えられる熱(例えばアニール処理等)を加えることにより、Mnが下地のSiと反応してマンガンシリケート(MnSiOx(ただし、xは3または4))からなる自己整合バリア膜205を形成することができる。すなわち、図5(a)に示すように、Mn膜204は、下地である層間絶縁膜202に含まれるSiと反応するので、図5(b)に示すように、バリア膜205を下地である層間絶縁膜202側に形成することができる。このため、ホールやトレンチのような凹部内でのバリア膜の体積を小さくすることができ、凹部内でのバリア膜の体積を0に近付けることができる。したがって、配線中のCuの体積を増加させて配線の低抵抗化を実現することができる。
RuはCuに対する濡れ性が高いため、Cuの下地にRuライナー膜を形成することにより、次のiPVDによるCu膜形成の際に、良好なCuの移動性を確保することができ、トレンチやホールの間口を塞ぐオーバーハングを生じ難くすることができる。このため、微細なトレンチまたはホールにもボイドを発生させずに確実にCuを埋め込むことができる。
Cu膜207は、PVDにより成膜されるが、上述したように、iPVD、例えばプラズマスパッタを用いることが好ましい。
この実験では、層間絶縁膜としてLow−k膜(SiCOH系;k=2.4))を用い、Low−k膜の表面に対して表面処理を行わなかったものと、N2プラズマ処理を行った後、過酸化水素系薬液処理を施す表面処理を行ったものについて265℃でデガス処理を行い、その後、デカカルボニル2マンガン(Mn2(CO)10)を用いたCVDにより300℃でMn膜を成膜した。
この実験では、図7に示すように、層間絶縁膜としてLow−k膜(SiCOH系;k=2.4))を用い、Low−k膜の表面に対して表面処理を行わなかったものと、TBOSL薬液に浸漬する表面処理を行ったものについて、Cu−1at%Mn合金膜をPVDにより200nmの厚さで成膜し、その上にPVDによりTa膜を10nmの厚さで成膜したサンプルを作製し、これらサンプルについて、200℃で1hrのアニールを施し、Low−k膜とCu−Mn合金膜との間にMnOを形成した後、自己整合バリアを形成するための400℃で30minのアニールを施した。
次に、本発明の実施形態に係るCu配線の形成方法の実施に好適な成膜システムについて説明する。図9は本発明の実施形態に係るCu配線の形成方法の実施に好適なシステムの概略構成を示すブロック図、図10は図9の成膜処理部を構成するマルチチャンバタイプの成膜システムの一例を示す平面図、図11は図9の制御部を示すブロック図である。
次に、Cu膜を形成するCu膜成膜装置22a,22bの好適な例について説明する。図12は、Cu膜成膜装置の一例を示す断面図である。
次に、Mn膜を形成するためのMn膜成膜装置12a(12b)について説明する。Mn膜は熱CVDにより好適に形成することができる。図13は、Mn膜成膜装置の一例を示す断面図であり、熱CVDによりMn膜を形成するものである。
Ruライナー膜成膜装置14a,14bは、成膜ガスを例えばルテニウムカルボニル(Ru3(CO)12)に変更するだけで、図13のMn成膜装置をそのまま用いることができ、これにより、ルテニウムカルボニルを熱分解させて熱CVDによるRuライナー膜の成膜を行うことができる。また、同じ装置を用いて上述したような他のCVD用原料によりRuライナー膜を成膜することもできる。
以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されることなく種々変形可能である。例えば、成膜処理部としては、図10のようなタイプに限らず、一つの搬送装置に全ての成膜装置が接続されているタイプであってもよい。また、図10のようなマルチチャンバタイプのシステムではなく、Mn膜、Ruライナー膜、Cu膜のうち、一部のみを同一の成膜システムで形成し、残部を別個に設けた装置により大気暴露を経て成膜するようにしてもよいし、全てを別個の装置で大気暴露を経て成膜するようにしてもよい。
14a,14b;Ruライナー膜成膜装置
22a,22b;Cu膜成膜装置
100;成膜システム
101;表面処理部
102;成膜処理部
103;CMP処理部
201;下部構造
202;層間絶縁膜(Si含有膜)
203;トレンチ
204;Mn膜
205;自己整合バリア膜
206;Ruライナー膜
207;Cu膜
208;Cu配線
W;半導体ウエハ(被処理基板)
Claims (9)
- 表面に所定パターンの凹部が形成されたSi含有膜を有する基板に対し、前記凹部を埋めるCu配線を形成するCu配線の形成方法であって、
少なくとも前記凹部の表面に、下地との反応で自己整合バリア膜となるMn膜をCVDにより形成する工程と、
Cu膜をPVDにより形成して前記凹部内に前記Cu膜を埋め込む工程と、
CMPにより全面を研磨して前記凹部内にCu配線を形成する工程と
を有することを特徴とするCu配線の形成方法。 - 前記Mn膜の成膜に先立って、前記Si含有膜の表面に、その表面が親水性の表面となるような表面処理を施すことを特徴とする請求項1に記載のCu配線の形成方法。
- 前記表面処理は、過酸化水素を含む薬液での処理を含むことを特徴とする請求項2に記載のCu配線の形成方法。
- 前記表面処理は、表面にOH基、H基またはNH基を形成することを特徴とする請求項2または請求項3に記載のCu配線の形成方法。
- 前記表面処理は、構造中にO−Si−OHを有する化合物での処理を含むことを特徴とする請求項2に記載のCu配線の形成方法。
- 前記Mn膜を成膜した後、前記Cu膜を形成する前に、Ru膜を形成する工程をさらに有することを特徴とする請求項1から請求項5のいずれか1項に記載のCu配線の形成方法。
- 前記Ru膜は、CVDにより形成されることを特徴とする請求項6に記載のCu配線の形成方法。
- 前記Cu膜の形成は、基板が収容された処理容器内にプラズマ生成ガスによりプラズマを生成し、Cuターゲットから粒子を飛翔させて、粒子を前記プラズマ中でイオン化させ、前記基板にバイアス電力を印加してイオンを基板上に引きこむ装置により行われることを特徴とする請求項1から請求項7のいずれか1項に記載のCu配線の形成方法。
- コンピュータ上で動作し、Cu配線形成システムを制御するためのプログラムが記憶された記憶媒体であって、前記プログラムは、実行時に、請求項1から請求項8のいずれかのCu配線の形成方法が行われるように、コンピュータに前記Cu配線形成システムを制御させることを特徴とする記憶媒体。
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KR20180068328A (ko) * | 2015-03-16 | 2018-06-21 | 도쿄엘렉트론가부시키가이샤 | 구리 배선의 제조 방법 |
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US10157784B2 (en) * | 2016-02-12 | 2018-12-18 | Tokyo Electron Limited | Integration of a self-forming barrier layer and a ruthenium metal liner in copper metallization |
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WO2017199767A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社アルバック | Cu膜の形成方法 |
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