JP2014075437A - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP2014075437A JP2014075437A JP2012221458A JP2012221458A JP2014075437A JP 2014075437 A JP2014075437 A JP 2014075437A JP 2012221458 A JP2012221458 A JP 2012221458A JP 2012221458 A JP2012221458 A JP 2012221458A JP 2014075437 A JP2014075437 A JP 2014075437A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 abstract description 8
- 238000009966 trimming Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 18
- 229910052782 aluminium Inorganic materials 0.000 description 18
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】第2の多結晶Si膜からなるヒューズ素子間に第1の多結晶Si膜からなるダミーヒューズとダミーヒューズ上に窒化膜を設けることで、多結晶Si膜からなるヒューズ素子の有無による層間膜の段差をなくし、ヒューズ開口領域の内側面と内部素子側の吸湿性のSOG膜が繋がることを防止し、より一層の信頼性向上を図る。
【選択図】図3
Description
前記半導体基板の表面に設けられた素子分離絶縁膜と、
前記素子分離絶縁膜の上に間隔を空けて配置された第1の多結晶シリコンからなる複数のダミーヒューズと、
前記複数のダミーヒューズを覆う窒化シリコン膜と、
前記窒化シリコン膜を介して、前記複数のダミーヒューズの間に配置された第2の多結晶シリコンからなるヒューズ素子と、
前記ヒューズ素子および前記複数のダミーヒューズの上に配置された絶縁膜と、
前記絶縁膜を介して、前記ヒューズ素子および前記複数のダミーヒューズの上に切れ目無く配置されたシールリングと、
前記絶縁膜に設けられた接続孔を介して前記ヒューズ素子に接続された第1配線層と、
前記第1配線層とその上方に配置された第2配線層との間に配置された第1金属間絶縁膜およびSOG膜および第2金属間絶縁膜と、
前記第2金属間絶縁膜の上に設けられた保護膜と、
前記保護膜を選択的に除去し、前記ヒューズ素子の上方に設けられたヒューズカットを容易に実施するための開口領域と、
を有する半導体集積回路装置とした。
図1に本発明の半導体装置の平面図、図2および図3に本発明の半導体装置の模式断面図を示す。
202 N型ウエル拡散層
203、503 素子分離絶縁膜
204、504 ゲート絶縁膜
205、405 第1の多結晶Si膜からなるゲート電極(ヒューズ素子)
106 第1の多結晶Si膜からなるダミーヒューズ
107 第1のSiN膜
108 第2の多結晶Si膜からなるヒューズ素子
209、509 抵抗体の低濃度領域
210、510 P型高濃度不純物領域
211、511 抵抗体の高濃度領域
212、512 高抵抗抵抗体
213、513 層間絶縁膜
214、514 BPSG膜
115、415 コンタクト孔
116、416 第1層目のアルミニウム膜(配線層)
117、317 第1層目のアルミニウム膜(シールリング)
218、518 第1層目の金属間絶縁膜
219、519 SOG膜
220、520 第2層目の金属間絶縁膜
221、521 第2のSiN膜
122、422 ヒューズ開口領域
Claims (2)
- 半導体基板と、
前記半導体基板の表面に設けられた素子分離絶縁膜と、
前記素子分離絶縁膜の上に間隔を空けて配置された第1の多結晶シリコンからなる複数のダミーヒューズと、
前記複数のダミーヒューズを覆う窒化シリコン膜と、
前記窒化シリコン膜を介して、前記複数のダミーヒューズの間に配置された第2の多結晶シリコンからなるヒューズ素子と、
前記ヒューズ素子および前記複数のダミーヒューズの上に配置された絶縁膜と、
前記絶縁膜を介して、前記ヒューズ素子および前記複数のダミーヒューズの上に切れ目無く配置されたシールリングと、
前記絶縁膜に設けられた接続孔を介して前記ヒューズ素子に接続された第1配線層と、
前記第1配線層とその上方に配置された第2配線層との間に配置された第1金属間絶縁膜およびSOG膜および第2金属間絶縁膜と、
前記第2金属間絶縁膜の上に設けられた保護膜と、
前記保護膜を選択的に除去し、前記ヒューズ素子の上方に設けられたヒューズカットを容易に実施するための開口領域と、
を有する半導体集積回路装置。 - 前記シールリングは前記第1配線層と同じ材料により、同時に形成されることを特徴とする請求項1記載の半導体集積回路装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012221458A JP6150997B2 (ja) | 2012-10-03 | 2012-10-03 | 半導体集積回路装置 |
TW102132993A TWI575697B (zh) | 2012-10-03 | 2013-09-12 | 半導體積體電路裝置 |
US14/041,022 US8937365B2 (en) | 2012-10-03 | 2013-09-30 | Semiconductor integrated circuit device |
CN201310455031.1A CN103715173B (zh) | 2012-10-03 | 2013-09-30 | 半导体集成电路装置 |
KR1020130117353A KR102095507B1 (ko) | 2012-10-03 | 2013-10-01 | 반도체 집적회로 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012221458A JP6150997B2 (ja) | 2012-10-03 | 2012-10-03 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014075437A true JP2014075437A (ja) | 2014-04-24 |
JP6150997B2 JP6150997B2 (ja) | 2017-06-21 |
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JP2012221458A Expired - Fee Related JP6150997B2 (ja) | 2012-10-03 | 2012-10-03 | 半導体集積回路装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8937365B2 (ja) |
JP (1) | JP6150997B2 (ja) |
KR (1) | KR102095507B1 (ja) |
CN (1) | CN103715173B (ja) |
TW (1) | TWI575697B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102471641B1 (ko) * | 2016-02-04 | 2022-11-29 | 에스케이하이닉스 주식회사 | 퓨즈구조 및 그를 포함하는 반도체장치 |
CN113410209B (zh) * | 2021-06-09 | 2023-07-18 | 合肥中感微电子有限公司 | 一种修调电路 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521605A (ja) * | 1991-07-12 | 1993-01-29 | Sony Corp | 半導体装置 |
JPH0722508A (ja) * | 1993-06-24 | 1995-01-24 | Hitachi Ltd | 半導体集積回路装置 |
JPH07321209A (ja) * | 1994-05-25 | 1995-12-08 | Nec Kyushu Ltd | 半導体記憶装置及びその製造方法 |
JPH09139431A (ja) * | 1995-11-15 | 1997-05-27 | Nec Corp | 半導体装置とその製造方法 |
JP2001185551A (ja) * | 1999-12-27 | 2001-07-06 | Oki Electric Ind Co Ltd | 半導体装置の構造及び製造方法 |
JP2002050692A (ja) * | 2000-08-01 | 2002-02-15 | Nec Corp | 半導体装置およびその製造方法 |
JP2012114258A (ja) * | 2010-11-25 | 2012-06-14 | Lapis Semiconductor Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1056066A (ja) * | 1996-08-08 | 1998-02-24 | Matsushita Electron Corp | アンチヒューズ素子およびその製造方法 |
JP2003086687A (ja) * | 2001-09-13 | 2003-03-20 | Seiko Epson Corp | 半導体装置 |
KR100476694B1 (ko) * | 2002-11-07 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 퓨즈 구조물 및 그 제조 방법 |
US8749020B2 (en) * | 2007-03-09 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal e-fuse structure design |
JP5616826B2 (ja) * | 2011-03-13 | 2014-10-29 | セイコーインスツル株式会社 | 抵抗回路を有する半導体装置 |
-
2012
- 2012-10-03 JP JP2012221458A patent/JP6150997B2/ja not_active Expired - Fee Related
-
2013
- 2013-09-12 TW TW102132993A patent/TWI575697B/zh not_active IP Right Cessation
- 2013-09-30 CN CN201310455031.1A patent/CN103715173B/zh not_active Expired - Fee Related
- 2013-09-30 US US14/041,022 patent/US8937365B2/en not_active Expired - Fee Related
- 2013-10-01 KR KR1020130117353A patent/KR102095507B1/ko active IP Right Grant
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0521605A (ja) * | 1991-07-12 | 1993-01-29 | Sony Corp | 半導体装置 |
JPH0722508A (ja) * | 1993-06-24 | 1995-01-24 | Hitachi Ltd | 半導体集積回路装置 |
JPH07321209A (ja) * | 1994-05-25 | 1995-12-08 | Nec Kyushu Ltd | 半導体記憶装置及びその製造方法 |
JPH09139431A (ja) * | 1995-11-15 | 1997-05-27 | Nec Corp | 半導体装置とその製造方法 |
JP2001185551A (ja) * | 1999-12-27 | 2001-07-06 | Oki Electric Ind Co Ltd | 半導体装置の構造及び製造方法 |
JP2002050692A (ja) * | 2000-08-01 | 2002-02-15 | Nec Corp | 半導体装置およびその製造方法 |
JP2012114258A (ja) * | 2010-11-25 | 2012-06-14 | Lapis Semiconductor Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103715173A (zh) | 2014-04-09 |
US20140091425A1 (en) | 2014-04-03 |
KR102095507B1 (ko) | 2020-03-31 |
US8937365B2 (en) | 2015-01-20 |
JP6150997B2 (ja) | 2017-06-21 |
TW201428930A (zh) | 2014-07-16 |
KR20140043872A (ko) | 2014-04-11 |
TWI575697B (zh) | 2017-03-21 |
CN103715173B (zh) | 2017-10-24 |
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