JP2013187440A - 縦型トレンチigbt及びその製造方法 - Google Patents
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
【解決手段】n−型Si基板1上にp型ボディ層3を形成する。p型ボディ層3を貫通するトレンチを形成し、トレンチ内にゲート絶縁膜5を介してトレンチゲート4を形成する。p型ボディ層3上にn型の不純物を含むポリシリコン膜16を形成する。ポリシリコン膜16からp型ボディ層3にn型の不純物を拡散させてp型ボディ層3上にn型エミッタ層6を形成する。n−型Si基板1の下面にp型コレクタ層13を形成する。
【選択図】図1
Description
図1は、本発明の実施の形態1に係る縦型トレンチIGBTを示す斜視図である。図2は、図1のA−A´に沿った断面図である。n−型Si基板1上にn型電荷蓄積層2とp型ボディ層3が順に設けられている。トレンチゲート4が、p型ボディ層3を貫通するトレンチ内にゲート絶縁膜5を介して設けられている。トレンチゲート4は平面視においてストライプ状に配置されている。
図14は、本発明の実施の形態2に係る縦型トレンチIGBTを示す斜視図である。図15は、図14のA−A´に沿った断面図である。膜厚500Å〜5000Åのポリシリコン膜20が、p型ボディ層3及びn型エミッタ層6とコンタクトプラグ11との間に設けられている。
3 p型ボディ層(ボディ層)
4 トレンチゲート
5 ゲート絶縁膜
6 n型エミッタ層(エミッタ層、真性エミッタ層)
7 n+型エミッタ層(エミッタ層、外部エミッタ層)
8 p+型拡散層(拡散層)
9 層間絶縁膜
10 エミッタ電極
11 コンタクトプラグ
13 p型コレクタ層(コレクタ層)
16,20 ポリシリコン膜
17 レジスト
18 自然酸化膜
21 容量の電極
22 ポリシリコン抵抗
Claims (9)
- 第1導電型の半導体基板上に第2導電型のボディ層を形成する工程と、
前記ボディ層を貫通するトレンチを形成し、前記トレンチ内にゲート絶縁膜を介してトレンチゲートを形成する工程と、
前記ボディ層上に第1導電型の不純物を含むポリシリコン膜を形成する工程と、
前記ポリシリコン膜から前記ボディ層に前記第1導電型の不純物を拡散させて前記ボディ層上に第1導電型のエミッタ層を形成する工程と、
前記半導体基板の下面に第2導電型のコレクタ層を形成する工程とを備えることを特徴とする縦型トレンチIGBTの製造方法。 - 後に前記エミッタ層を形成する領域において前記ポリシリコン膜上にレジストを形成する工程と、
前記レジストをマスクとして前記ポリシリコン膜をエッチングする工程と、
前記ポリシリコン膜をエッチングした後に、前記レジストをマスクとして前記ボディ層に第2導電型の不純物を注入する工程と、
熱処理を行って前記ボディ層の前記第2導電型の不純物を注入した領域に第2導電型の拡散層を形成する工程とを更に備えることを特徴とする請求項1に記載の縦型トレンチIGBTの製造方法。 - 前記ポリシリコン膜のグレインサイズは前記エミッタ層の幅より小さいことを特徴とする請求項1又は2に記載の縦型トレンチIGBTの製造方法。
- 前記ボディ層と前記ポリシリコン膜の間に自然酸化膜が形成されていることを特徴とする請求項1〜3の何れか1項に記載の縦型トレンチIGBTの製造方法。
- 前記ポリシリコン膜を、前記トレンチゲートを構成するポリシリコンと同時に形成することを特徴とする請求項1〜4の何れか1項に記載の縦型トレンチIGBTの製造方法。
- 前記ポリシリコン膜を、容量の電極を構成するポリシリコンと同時に形成することを特徴とする請求項1〜5の何れか1項に記載の縦型トレンチIGBTの製造方法。
- 前記ポリシリコン膜をポリシリコン抵抗と同時に形成することを特徴とする請求項1〜6の何れか1項に記載の縦型トレンチIGBTの製造方法。
- 前記エミッタ層は、
前記トレンチゲートの近傍に形成された真性エミッタ層と、
前記真性エミッタ層を外部に引き出す外部エミッタ層とを有することを特徴とする請求項1〜7の何れか1項に記載の縦型トレンチIGBTの製造方法。 - 第1導電型の半導体基板と、
前記半導体基板上に設けられた第2導電型のボディ層と、
前記ボディ層を貫通するトレンチ内にゲート絶縁膜を介して設けられたトレンチゲートと、
前記ボディ層上に設けられた第1導電型のエミッタ層と、
前記半導体基板の下面に設けられた第2導電型のコレクタ層と、
前記トレンチゲートを覆う層間絶縁膜と、
前記層間絶縁膜上に設けられたエミッタ電極と、
前記層間絶縁膜を貫通して前記ボディ層及び前記エミッタ層と前記エミッタ電極とを接続するコンタクトプラグと、
前記ボディ層及び前記エミッタ層の少なくとも一方と前記コンタクトプラグとの間に設けられたポリシリコン膜とを備えることを特徴とする縦型トレンチIGBT。
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JP2012052580A JP5754397B2 (ja) | 2012-03-09 | 2012-03-09 | 縦型トレンチigbtの製造方法 |
US13/619,395 US8841175B2 (en) | 2012-03-09 | 2012-09-14 | Vertical trench IGBT and method for manufacturing the same |
CN201210434810.9A CN103311121B (zh) | 2012-03-09 | 2012-11-05 | 纵型沟槽igbt及其制造方法 |
DE102012220166.1A DE102012220166B4 (de) | 2012-03-09 | 2012-11-06 | Verfahren zur Herstellung eines IGBT mit vertikalen Gräben |
KR1020130019631A KR101444081B1 (ko) | 2012-03-09 | 2013-02-25 | 종형 트렌치 igbt 및 그 제조방법 |
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US9257544B2 (en) | 2014-04-25 | 2016-02-09 | Fuji Electric Co., Ltd. | Semiconductor device and fabrication method of semiconductor device |
JP2016033993A (ja) * | 2014-07-31 | 2016-03-10 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US11094787B2 (en) | 2018-06-22 | 2021-08-17 | Fuji Electric Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device |
US11127844B2 (en) | 2015-02-03 | 2021-09-21 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
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US9583605B2 (en) * | 2015-02-05 | 2017-02-28 | Changzhou ZhongMin Semi-Tech Co. Ltd | Method of forming a trench in a semiconductor device |
JP6319508B2 (ja) | 2015-02-16 | 2018-05-09 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2019102669A (ja) * | 2017-12-04 | 2019-06-24 | 株式会社東芝 | 半導体装置 |
CN110190119A (zh) * | 2018-02-22 | 2019-08-30 | 三垦电气株式会社 | 半导体装置和电子设备 |
CN115411101A (zh) * | 2022-07-22 | 2022-11-29 | 上海林众电子科技有限公司 | 一种多晶硅发射极igbt器件、制备方法及其应用 |
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KR101444081B1 (ko) | 2014-09-26 |
JP5754397B2 (ja) | 2015-07-29 |
KR20130103358A (ko) | 2013-09-23 |
US8841175B2 (en) | 2014-09-23 |
CN103311121A (zh) | 2013-09-18 |
DE102012220166B4 (de) | 2016-02-25 |
US20130234200A1 (en) | 2013-09-12 |
DE102012220166A1 (de) | 2013-09-12 |
CN103311121B (zh) | 2016-12-21 |
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