JP2013122759A5 - - Google Patents

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JP2013122759A5
JP2013122759A5 JP2012268484A JP2012268484A JP2013122759A5 JP 2013122759 A5 JP2013122759 A5 JP 2013122759A5 JP 2012268484 A JP2012268484 A JP 2012268484A JP 2012268484 A JP2012268484 A JP 2012268484A JP 2013122759 A5 JP2013122759 A5 JP 2013122759A5
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operating frequency
frequency
state
functional block
operating
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JP2012268484A
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JP5997029B2 (ja
JP2013122759A (ja
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JP2012268484A 2011-12-12 2012-12-07 機能ブロックを含むＳｏＣのクロック制御方法、それを具現したＳｏＣ、及びそれを含む半導体システム Active JP5997029B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2011-0133195 2011-12-12
KR1020110133195A KR101851614B1 (ko) 2011-12-12 2011-12-12 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템
US13/687637 2012-11-28
US13/687,637 US8928385B2 (en) 2011-12-12 2012-11-28 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

Publications (3)

Publication Number Publication Date
JP2013122759A JP2013122759A (ja) 2013-06-20
JP2013122759A5 true JP2013122759A5 (enExample) 2015-11-19
JP5997029B2 JP5997029B2 (ja) 2016-09-21

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JP2012268484A Active JP5997029B2 (ja) 2011-12-12 2012-12-07 機能ブロックを含むＳｏＣのクロック制御方法、それを具現したＳｏＣ、及びそれを含む半導体システム

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US (2) US8928385B2 (enExample)
JP (1) JP5997029B2 (enExample)
KR (1) KR101851614B1 (enExample)
CN (1) CN103163940B (enExample)
TW (1) TWI564705B (enExample)

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