JP5997029B2 - 機能ブロックを含むSoCのクロック制御方法、それを具現したSoC、及びそれを含む半導体システム - Google Patents

機能ブロックを含むSoCのクロック制御方法、それを具現したSoC、及びそれを含む半導体システム Download PDF

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JP5997029B2
JP5997029B2 JP2012268484A JP2012268484A JP5997029B2 JP 5997029 B2 JP5997029 B2 JP 5997029B2 JP 2012268484 A JP2012268484 A JP 2012268484A JP 2012268484 A JP2012268484 A JP 2012268484A JP 5997029 B2 JP5997029 B2 JP 5997029B2
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JP2013122759A (ja
JP2013122759A5 (enExample
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東 根 金
東 根 金
純 ▲チョル▼ 權
純 ▲チョル▼ 權
時 永 金
時 永 金
宰 坤 李
宰 坤 李
▲ジュン▼ 訓 許
▲ジュン▼ 訓 許
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/04Shaping pulses by increasing duration; by decreasing duration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/08Output circuits
    • H03K21/10Output circuits comprising logic circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19Monitoring patterns of pulse trains
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/50Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Manipulation Of Pulses (AREA)
JP2012268484A 2011-12-12 2012-12-07 機能ブロックを含むSoCのクロック制御方法、それを具現したSoC、及びそれを含む半導体システム Active JP5997029B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020110133195A KR101851614B1 (ko) 2011-12-12 2011-12-12 기능블럭을 포함하는 SoC의 클락 제어 방법, 이를 구현한 SoC 및 이를 포함하는 반도체 시스템
KR10-2011-0133195 2011-12-12
US13/687637 2012-11-28
US13/687,637 US8928385B2 (en) 2011-12-12 2012-11-28 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

Publications (3)

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JP2013122759A JP2013122759A (ja) 2013-06-20
JP2013122759A5 JP2013122759A5 (enExample) 2015-11-19
JP5997029B2 true JP5997029B2 (ja) 2016-09-21

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JP2012268484A Active JP5997029B2 (ja) 2011-12-12 2012-12-07 機能ブロックを含むSoCのクロック制御方法、それを具現したSoC、及びそれを含む半導体システム

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US (2) US8928385B2 (enExample)
JP (1) JP5997029B2 (enExample)
KR (1) KR101851614B1 (enExample)
CN (1) CN103163940B (enExample)
TW (1) TWI564705B (enExample)

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Also Published As

Publication number Publication date
US8928385B2 (en) 2015-01-06
US20150084675A1 (en) 2015-03-26
CN103163940B (zh) 2017-10-03
TW201331748A (zh) 2013-08-01
KR20130066398A (ko) 2013-06-20
TWI564705B (zh) 2017-01-01
CN103163940A (zh) 2013-06-19
KR101851614B1 (ko) 2018-06-12
US20130147526A1 (en) 2013-06-13
JP2013122759A (ja) 2013-06-20
US9054680B2 (en) 2015-06-09

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