KR101851614B1 - 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템 - Google Patents

기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템 Download PDF

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KR101851614B1
KR101851614B1 KR1020110133195A KR20110133195A KR101851614B1 KR 101851614 B1 KR101851614 B1 KR 101851614B1 KR 1020110133195 A KR1020110133195 A KR 1020110133195A KR 20110133195 A KR20110133195 A KR 20110133195A KR 101851614 B1 KR101851614 B1 KR 101851614B1
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South Korea
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frequency
state
functional block
mode
clock
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KR20130066398A (ko
Inventor
김동근
권순철
김시영
이재곤
허정훈
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삼성전자주식회사
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Priority to KR1020110133195A priority Critical patent/KR101851614B1/ko
Priority to US13/687,637 priority patent/US8928385B2/en
Priority to DE102012111916A priority patent/DE102012111916A1/de
Priority to JP2012268484A priority patent/JP5997029B2/ja
Priority to TW101146938A priority patent/TWI564705B/zh
Priority to CN201210535320.8A priority patent/CN103163940B/zh
Publication of KR20130066398A publication Critical patent/KR20130066398A/ko
Priority to US14/559,131 priority patent/US9054680B2/en
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Publication of KR101851614B1 publication Critical patent/KR101851614B1/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H03K21/10—Output circuits comprising logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Manipulation Of Pulses (AREA)
KR1020110133195A 2011-12-12 2011-12-12 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템 Active KR101851614B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1020110133195A KR101851614B1 (ko) 2011-12-12 2011-12-12 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템
US13/687,637 US8928385B2 (en) 2011-12-12 2012-11-28 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same
JP2012268484A JP5997029B2 (ja) 2011-12-12 2012-12-07 機能ブロックを含むＳｏＣのクロック制御方法、それを具現したＳｏＣ、及びそれを含む半導体システム
DE102012111916A DE102012111916A1 (de) 2011-12-12 2012-12-07 Verfahren zum Steuern von Taktsignalen bei einem Ein-Chip-System mit Funktionsblöcken, Ein-Chip-Systeme und Halbleitersysteme mit denselben
TW101146938A TWI564705B (zh) 2011-12-12 2012-12-12 系統晶片以及其操作方法
CN201210535320.8A CN103163940B (zh) 2011-12-12 2012-12-12 片上系统时钟控制方法、片上系统及包括其的半导体系统
US14/559,131 US9054680B2 (en) 2011-12-12 2014-12-03 Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110133195A KR101851614B1 (ko) 2011-12-12 2011-12-12 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템

Publications (2)

Publication Number Publication Date
KR20130066398A KR20130066398A (ko) 2013-06-20
KR101851614B1 true KR101851614B1 (ko) 2018-06-12

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KR1020110133195A Active KR101851614B1 (ko) 2011-12-12 2011-12-12 기능블럭을 포함하는 ＳｏＣ의 클락 제어 방법, 이를 구현한 ＳｏＣ 및 이를 포함하는 반도체 시스템

Country Status (5)

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US (2) US8928385B2 (enExample)
JP (1) JP5997029B2 (enExample)
KR (1) KR101851614B1 (enExample)
CN (1) CN103163940B (enExample)
TW (1) TWI564705B (enExample)

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US11646067B2 (en) 2021-02-18 2023-05-09 SK Hynix Inc. Data storage device and operating method thereof

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CN103163940A (zh) 2013-06-19
CN103163940B (zh) 2017-10-03
US20130147526A1 (en) 2013-06-13
US9054680B2 (en) 2015-06-09
JP5997029B2 (ja) 2016-09-21
TW201331748A (zh) 2013-08-01
US8928385B2 (en) 2015-01-06
TWI564705B (zh) 2017-01-01
JP2013122759A (ja) 2013-06-20
US20150084675A1 (en) 2015-03-26
KR20130066398A (ko) 2013-06-20

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