WO2009013860A1 - デジタルｐｌｌ装置 - Google Patents

デジタルｐｌｌ装置 Download PDF

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Publication number
WO2009013860A1
WO2009013860A1 PCT/JP2008/001827 JP2008001827W WO2009013860A1 WO 2009013860 A1 WO2009013860 A1 WO 2009013860A1 JP 2008001827 W JP2008001827 W JP 2008001827W WO 2009013860 A1 WO2009013860 A1 WO 2009013860A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
frequency
input clock
input
selects
Prior art date
Application number
PCT/JP2008/001827
Other languages
English (en)
French (fr)
Inventor
Syuji Kato
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to JP2008554553A priority Critical patent/JP4625867B2/ja
Priority to US12/439,644 priority patent/US7948290B2/en
Priority to CN2008800006443A priority patent/CN101542908B/zh
Publication of WO2009013860A1 publication Critical patent/WO2009013860A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　入力クロック分周手段（5）は、入力クロックを分周し、入力クロック逓倍手段（6）は入力クロックを逓倍する。動作クロック選択手段（7）は、周波数検知手段（8）の周波数検知結果に基づいて、入力クロックが高速な場合には分周されたクロックを選択する一方で低速な場合には逓倍されたクロックを選択して動作クロックとして位相比較手段（2）に出力する。位相比較手段（2）は、分周又は逓倍されたクロックで動作し、基準信号と比較信号の位相差をゼロにするよう発振手段（3）を制御して出力クロックを追従させる。
PCT/JP2008/001827 2007-07-23 2008-07-08 デジタルｐｌｌ装置 WO2009013860A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008554553A JP4625867B2 (ja) 2007-07-23 2008-07-08 デジタルｐｌｌ装置
US12/439,644 US7948290B2 (en) 2007-07-23 2008-07-08 Digital PLL device
CN2008800006443A CN101542908B (zh) 2007-07-23 2008-07-08 数字pll装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-190405 2007-07-23
JP2007190405 2007-07-23

Publications (1)

Publication Number Publication Date
WO2009013860A1 true WO2009013860A1 (ja) 2009-01-29

Family

ID=40281122

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001827 WO2009013860A1 (ja) 2007-07-23 2008-07-08 デジタルｐｌｌ装置

Country Status (4)

Country Link
US (1) US7948290B2 (ja)
JP (1) JP4625867B2 (ja)
CN (1) CN101542908B (ja)
WO (1) WO2009013860A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072847A (ja) * 2012-10-01 2014-04-21 Fujitsu Semiconductor Ltd クロック生成装置、クロック生成装置の動作方法およびシステム

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US8063986B2 (en) * 2007-06-04 2011-11-22 Himax Technologies Limited Audio clock regenerator with precisely tracking mechanism
CN102187579A (zh) * 2008-10-23 2011-09-14 松下电器产业株式会社 数字pll电路及通信装置
JP6195444B2 (ja) * 2013-01-18 2017-09-13 サターン ライセンシング エルエルシーＳａｔｕｒｎ Ｌｉｃｅｎｓｉｎｇ ＬＬＣ ソース機器、通信システム、ソース機器の制御方法およびシンク機器の制御方法
CN104579325B (zh) * 2013-10-10 2017-09-05 瑞昱半导体股份有限公司 数据接收装置与方法
CN105406859A (zh) * 2015-12-10 2016-03-16 武汉理工大学 单片全数字锁相环
CN108762374A (zh) * 2018-05-29 2018-11-06 西安微电子技术研究所 一种时钟管理电路及基于该电路的服务级芯片
CN113016139B (zh) * 2019-10-21 2024-03-29 京东方科技集团股份有限公司 用于产生高比率倍频时钟信号的数字时钟电路

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JP2003347933A (ja) * 2002-05-30 2003-12-05 Matsushita Electric Ind Co Ltd クロック生成回路
JP2007082001A (ja) * 2005-09-15 2007-03-29 Rohm Co Ltd クロック生成回路、およびそれを搭載した電子機器

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US5028887A (en) * 1989-08-31 1991-07-02 Qualcomm, Inc. Direct digital synthesizer driven phase lock loop frequency synthesizer with hard limiter
JP2926900B2 (ja) * 1990-06-01 1999-07-28 ソニー株式会社 ディスク再生装置
EP0691746A1 (en) * 1993-03-18 1996-01-10 Kabushiki Kaisha Toshiba Frequency synthesizer
JPH1022822A (ja) * 1996-07-05 1998-01-23 Sony Corp ディジタルｐｌｌ回路
JP3433021B2 (ja) * 1996-09-20 2003-08-04 パイオニア株式会社 Ｐｌｌ回路
US5952890A (en) * 1997-02-05 1999-09-14 Fox Enterprises, Inc. Crystal oscillator programmable with frequency-defining parameters
US5834987A (en) * 1997-07-30 1998-11-10 Ercisson Inc. Frequency synthesizer systems and methods for three-point modulation with a DC response
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US6005443A (en) * 1998-03-19 1999-12-21 Conexant Systems, Inc. Phase locked loop frequency synthesizer for multi-band application
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US6111470A (en) * 1998-10-09 2000-08-29 Philips Electronics North America Corporation Phase-locked loop circuit with charge pump noise cancellation
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CA2293173A1 (en) * 1999-12-29 2001-06-29 Nortel Networks Corporation Agile phase noise filter using vcxo and frequency synthesis
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10224336A (ja) * 1997-02-10 1998-08-21 Oki Electric Ind Co Ltd 位相同期回路及び位相同期方法
JP2003347933A (ja) * 2002-05-30 2003-12-05 Matsushita Electric Ind Co Ltd クロック生成回路
JP2007082001A (ja) * 2005-09-15 2007-03-29 Rohm Co Ltd クロック生成回路、およびそれを搭載した電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072847A (ja) * 2012-10-01 2014-04-21 Fujitsu Semiconductor Ltd クロック生成装置、クロック生成装置の動作方法およびシステム

Also Published As

Publication number Publication date
CN101542908A (zh) 2009-09-23
US7948290B2 (en) 2011-05-24
JP4625867B2 (ja) 2011-02-02
JPWO2009013860A1 (ja) 2010-09-30
US20100001773A1 (en) 2010-01-07
CN101542908B (zh) 2012-10-03

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