JP2011248579A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2011248579A5 JP2011248579A5 JP2010120371A JP2010120371A JP2011248579A5 JP 2011248579 A5 JP2011248579 A5 JP 2011248579A5 JP 2010120371 A JP2010120371 A JP 2010120371A JP 2010120371 A JP2010120371 A JP 2010120371A JP 2011248579 A5 JP2011248579 A5 JP 2011248579A5
- Authority
- JP
- Japan
- Prior art keywords
- clock
- signal
- supply
- during
- circuit blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 4
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010120371A JP5662701B2 (ja) | 2010-05-26 | 2010-05-26 | クロック供給装置 |
| US13/113,823 US8487672B2 (en) | 2010-05-26 | 2011-05-23 | Clock supply apparatus |
| US13/914,326 US8698526B2 (en) | 2010-05-26 | 2013-06-10 | Clock supply apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010120371A JP5662701B2 (ja) | 2010-05-26 | 2010-05-26 | クロック供給装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011248579A JP2011248579A (ja) | 2011-12-08 |
| JP2011248579A5 true JP2011248579A5 (enExample) | 2013-07-04 |
| JP5662701B2 JP5662701B2 (ja) | 2015-02-04 |
Family
ID=45021579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010120371A Active JP5662701B2 (ja) | 2010-05-26 | 2010-05-26 | クロック供給装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US8487672B2 (enExample) |
| JP (1) | JP5662701B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2596412B1 (en) * | 2010-07-20 | 2018-01-03 | NXP USA, Inc. | Electronic circuit, safety critical system, and method for providing a reset signal |
| TWI568182B (zh) * | 2012-03-09 | 2017-01-21 | 鈺創科技股份有限公司 | 輸入接收電路及其操作方法 |
| US9419630B2 (en) * | 2014-12-29 | 2016-08-16 | Texas Instruments Incorporated | Phase shifted coarse/fine clock dithering responsive to controller select signals |
| KR102387466B1 (ko) * | 2015-09-18 | 2022-04-15 | 삼성전자주식회사 | 반도체 장치 |
| CN106992770B (zh) * | 2016-01-21 | 2021-03-30 | 华为技术有限公司 | 时钟电路及其传输时钟信号的方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2040628A (en) * | 1979-01-29 | 1980-08-28 | Control Data Corp | A clock pulse circuit |
| JPH02292613A (ja) * | 1989-05-02 | 1990-12-04 | Hitachi Ltd | N倍周期クロック生成方式および回路ならびに情報処理システム |
| JP3119628B2 (ja) | 1998-08-21 | 2000-12-25 | 甲府日本電気株式会社 | 消費電力低減回路 |
| JP2001005552A (ja) * | 1999-06-18 | 2001-01-12 | Nec Eng Ltd | 消費電力低減回路 |
| JP2003256068A (ja) * | 2002-03-04 | 2003-09-10 | Seiko Epson Corp | クロック制御システム |
| JP2004110718A (ja) * | 2002-09-20 | 2004-04-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置のリセット方法及び半導体集積回路装置 |
| JP2005157883A (ja) * | 2003-11-27 | 2005-06-16 | Oki Electric Ind Co Ltd | リセット回路 |
| JP2009054031A (ja) * | 2007-08-28 | 2009-03-12 | Toshiba Corp | リセット制御装置 |
-
2010
- 2010-05-26 JP JP2010120371A patent/JP5662701B2/ja active Active
-
2011
- 2011-05-23 US US13/113,823 patent/US8487672B2/en active Active
-
2013
- 2013-06-10 US US13/914,326 patent/US8698526B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI571060B (zh) | 重覆單一循環脈衝寬度調變之產生 | |
| TWI568187B (zh) | 與可變頻率成比例之多相位脈衝寬度調變之產生 | |
| JP2011248579A5 (enExample) | ||
| JP2015522800A5 (enExample) | ||
| JP2008157971A5 (enExample) | ||
| TWI556583B (zh) | 同步多頻率脈衝寬度調變產生器 | |
| JP2011071995A5 (ja) | カウンタ回路 | |
| EP2879017A3 (en) | Performing an operating frequency change using a dynamic clock control technique | |
| JP2011061457A5 (enExample) | ||
| JP2012108729A5 (enExample) | ||
| JP2010103680A5 (enExample) | ||
| JP2013149310A5 (enExample) | ||
| JP2014116946A5 (enExample) | ||
| JP2017507323A5 (enExample) | ||
| JP2014520436A5 (enExample) | ||
| JP2015518357A5 (enExample) | ||
| JP2016045329A5 (enExample) | ||
| JP2010282399A5 (enExample) | ||
| JP2015515769A5 (enExample) | ||
| JP2015502700A5 (enExample) | ||
| WO2013126626A3 (en) | High resolution pulse width modulator | |
| JP2013046268A (ja) | クロック分周装置 | |
| JP2015099146A5 (enExample) | ||
| WO2013029867A3 (en) | Method for generating a pulse signal sequence | |
| EP3958464A3 (en) | Phase synchronized lo generation |