GB2040628A - A clock pulse circuit - Google Patents

Abstract

A clock network for LSI chips of a data handling network comprises a pulse producing circuit on each LSI chip (12, 14) responsive to the leading edge of a master clock signal to produce local clock signals whose pulse durations are dependent, at least in part, on the manufacturing and environmental conditions of the LSI chip.The pulse producing circuit on each LSI chip consists of a plurality of delay networks (22, 24, 26; 22a, 24a, 26a) and a NOR gate (28; 28a), so arranged that the gate is set to produce the leading edge of the local clock pulse coincident with the leading edge of the master clock pulse, and will produce the trailing edge of the local clock pulse upon a delay dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the chip and the environmental conditions to which the chip is subjected. <IMAGE>

Description

SPECIFICATION A clock pulse circuit This invention relates to clock pulses circuits e.g. for clocking of large scale integrated (LSI) circuits for use in data handling-networks, for example, distribution and data processing systems.

It is common in data processing or distribution systems to provide master clocks which provide clock pulses for clocking individual circuits of the data processing or distribution system. For example, a single master clock might itself drive slave clocks for clocking individual circuits of the data processing or distribution system. Ordinarily, the data processing or distribution systems will include a plurality of circuits, some or all of which may be LSI circuits. In a typical system, a slave clock will operate a plurality of LSI chips. In the past it has been difficult to control clock pulsing in LSI chips, largely due to manufacturing and environmental differences between the individual LSI chips in the data processing or distribution system. For example. latch circuits on certain LSI chips might be capable of responding to clock pulses at different rates than latch circuits on other LSI chips simply due to manufacturing and environmental conditions to which the LSI chip is subjected. Consequently, some latch circuits in a data processing or distribution system might respond more quickly to clock pulses than other latch circuits.

It has been the practice to design the master clock in such a way that the clock pulses are wide or long enough to set all latch circuits. Thus, when a latch circuit responds to a clock pulse to accomplish a "set" condition, the latch circuit produces a latch signal which is fed back upon itself as an input to the circuit to hold the latch circuit in a set condition after the clock pulse is removed. However, if the clock pulse is too short, the clock pulse may not be present when the latch signal is returned to the input of the latch circuit, thereby resulting in a false non-setting of the latch circuit. On the other hand, if the clock pulse is too long, the latch signal may "AND" with the clock signal thereby producing an undesirable "racing" condition and produce a false setting of the latch circuit. Consequently, it has been necessary to design the master clock in such a manner that the clock pulse is narrow or short enough to prevent racing. Thus, in data processing or distribution systems, master clocks had to be designed so that the pulses were long enough to assure setting of even the slowest latch circuit, yet short enough to prevent racing of the fastest latch circuit.

Furthermore, degradation of the pulse signal occurred in both the slave clock and the clock distribution, thereby affecting the ability of a particular LSI circuit to respond to a clock signal.

According to one aspect of the present invention there is provided a clock pulse circuit for providing local clock pulses for a plurality of large scale integrated circuits, each contained on respective ones of a plurality of integrated circuit chips, the clock pulse circuit comprising: master clock means for producing master clock pulses having leading edges occurring at a predetermined frequency; pulse producing means for each of said integrated circuit chips, each pulse producing means being responsive to the leading edges of said master clock pulses for producing local clock pulses for the circuit on the respective integrated circuit chip, said local clock pulses being at said predetermined frequency and having pulse durations dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the respective integrated circuit chip and the environmental conditions to which the integrated circuit chip is subjected; and means connecting said master clock means to each of said pulse producing means.

Each pulse producing means may include a plurality of serially arranged delay circuits and a gate circuit, said serially arranged delay circuits being responsive to the leading edge of each master clock pulse to produce a respective delayed pulse having a leading edge, and said gate circuit being responsive to the leading edge of each master clock pulse to produce the leading edge of said local clock pulse and being responsive to the leading edge of each delayed pulse to produce the trailing edge of said local clock pulse.

According to another aspect of the present invention there is provided a data handling network comprising: a plurality of large scale integrated circuits, each contained on respective ones of a plurality of integrated circuit chips; and a clock pulse circuit for deriving local clock pulses for the circuits on each respective integrated circuit chip, the clock pulse circuit comprising master clock means for producing master clock pulses having leading edges occurring at a predetermined frequency, pulse producing means on each of said integrated circuit chips responsive to the leading edge of said master clock pulses for producing local clock pulses for the circuit on the respective integrated circuit chip, said local clock pulses being at said predetermined frequency and having pulse durations dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the respective integrated circuit chip and the environmental conditions to which the integrated circuit chip is subjected, and means connecting said master clock means to each of said pulse producing means.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 is a block circuit diagram of one embodiment of a clock pulse circuit according to the present invention for a plurality of LSI chips in a date handling network; and Figure 2 shows waveforms illustrating the operation of the clock pulse circuit of Figure 1.

Referring to the drawings, and particularly Figure 1, there is illustrated one embodiment of a clock pulse circuit according to the present invention, including a master clock 10 connected to LSI chips 12, 14 by means of respective electrical leads 1 6, 1 8. By way of example, the electrical leads 1 6, 1 8 may be ordinary hard wire connections to the LSI chips through suitable connector mechanisms (not shown). A clocking network on each LSI chip is essentially the same.

The clocking network on the LSI chip 1 2 consists of an inverter 20, a plurality of delay circuits 22, 24, 26 and a NOR gate 28. The clocking network on the LSI chip 14 consists of an inverter 20a, a plurality of delay circuits 22a, 24a, 26a, and a NOR gate 28a. An incoming signal from the master clock 10 is connected, as an input, to the inverter 20 and the NOR gate 28 of the clocking network on the LSl chip 12 and, as an input, to the inverter 20a and the NOR gate 28a of the clocking network on the LSl chip 1 4. The inverter 20 provides its output through the succession of delay circuits 22, 24, 26 to the other input of the NOR gate 28 and the inverter 20a provides its output through the succession of delay circuits 22a, 24a, 26a to the other input of the NOR gate 28a.

The operation of the clock pulse circuit may best be explained with reference to Figure 2. The master clock 10 produces a signal waveform 30.

The signal waveform 30 has leading edges 31, 32 and is supplied directly to the input inverters 20, 20a in which the signal waveforms are inverted.

The inverted signal waveforms are fed to the respective delay circuits 22, 22a. The signal waveform 30 is also fed to one input of each of the NOR gates 28, 28a. For the purposes of explanation, it is assumed that the clocking networks on the LSI chips 12, 14 are in all respects identical, except for the manufacturing and environmental conditions to which the chips were subjected.

For the purpose of illustration, it will be assumed that the manufacturing and/or environmental tolerance and/or conditions of LSI chips 12, 14 are, or were, different, such that the LSI chip 12 responds more slowly to an input signal than the LSI chip 14. Hence, on the LSI chip 12, the inverted signal waveform 30 is delayed through a succession of delay periods provided by the delay circuits 22, 24, 26 to form signal waveforms A, B, C, respectively; the signal waveform A being delayed relative to the signal waveform 30 by the delay circuit 22 for a delay period A, the signal waveform B being delayed relative to the signal waveform A by the delay circuit 24 for a delay period B; and the signal waveform C being delayed relative to the signal waveform B by the delay circuit 26 for a delay period C. Hence leading edges 33, 34 of the signal waveform C are delayed from corresponding leading edges 31, 32 of the signal waveform 30 by a total delay period equal to the arithmetic sum of the delay periods A, B and C. Similarly, on the LSl chip 14, the inverted signal waveform 30 is delayed through a succession of delay periods provided by the delay circuits 22a, 24a, 26a to form signal waveforms E, F, G respectively; the signal waveform E being delayed relative to the signal waveform 30 by the delay circuit 22a for a delay period E; the signal waveform F being delayed relative to the signal waveform E by the delay circuit 24a for a delay period F; and the signal waveform G being delayed from the signal waveform F by the delay circuit 26a for a delay period G. Hence, leading edges 35, 36 of the signal waveform G are delayed from corresponding leading edges 31, 32 of the signal waveform 30 by a total delay period equal to the arithmetic sum of the delay periods E, F, G.

The NOR gates 28, 28a both respond to the leading edges 31, 32 of the signal waveform 30 to "set" to a low condition. The NOR gate 28 is reset to a high condition by each leading edge 33, 34 of the signal waveform C, thereby producing local clock pulses (signal waveform D). On the other hand the NOR gate 28a is reset to a high condition by each leading 36, 36 of the signal waveform G, thereby producing local clock pulses (signal waveform H). Thus the signal waveforms D, H have their leading edges synchronized with the master clock pulses and at the same frequency as the master clock frequency, but the pulse duration is dependent, in part, upon the manufacturing and environmental conditions of the respective LSI chips 12, 14. This is visually evident from Figure 2 where the pulse duration of the signal waveform H is shorter than that of the signal waveform D. This is caused by the fact that manufacturing and/or environmental conditions of the LSI chips 1 2, 14 are such that the LSI chip 12 responds more slowly to input signals than the LSI chip 14.

It is important to the proper operation of the clock pulse circuit illustrated in Figure 1 that the pulse duration of the signal waveform 30 (that is, the time duration between each leading edge 31, 32 and each trailing edge 37, 38 of the master clock pulses) is greater than the longest pulse duration of the local clock pulses produced by any LSl chip. This condition is necessary because if the trailing edge 37 occurred before the leading edge (i.e. leading edge 33) of the last delay signal waveform of a LSI chip, the resulting local clock pulse (signal waveform D) would have its trailing edge coincident with the trailing edge of the signal waveform 30, which would probably be of too short a duration for proper operation of the LSI chip. However, the requirement that the master clock pulses be adequately long actually results in advantage, namely that the signal waveform may be transferred through relatively large digital networks without concern for degradation of its pulse length. Hence, because the duration of the local clock pulses is independent of the duration of the master clock pulses, a minimum of logic is necessary to transform the master clock pulses to the local clock pulses.

Since other circuits (not shown) on the LSI chips 12, 14 are manufactured simultaneously with the clocking networks on the respective LSI chips (because they reside on the same semiconductor die with the clocking networks), and since the environmental conditions to which each LSl chip is subjected is essentially uniform for the individual LSI chip, the local clock pulses are tailored for the circuits on the respective chip.

It will be appreciated that whilst the clock pulse circuit described above provides each LSl chip with three delay circuits, the actual number of delay circuits for each LSI chip depends upon the particular application. Furthermore, it may be desirable to "tap" between delay circuits in some cases to produce several clock pulse signals on a particular chip having different pulse durations for different applications. Further, while the local clock signals are described as negative or "lowgoing" signals, signal reversal may be accomplished utilising well-known techniques.

The clock pulse circuit according to the present invention and described above thus provides a simple, reliable technique for tailoring local clock signals for circuits on LSI chips. Hence, those LSI chips whose tolerances are such as to react more rapidly to clock pulses will, as a consequence, have a delay circuit producing a shorter delay, and thereby producing narrower local clock pulses than LSI chips tending to react more slowly. Thus the clock pulse circuit produces local clock pulses for each LSI chip tailored precisely to the capabilities of the LSI chip itself. Moreover problems heretofore associated with false settings and "racing" of data handling networks may be substantially reduced, or even eliminated. The clock pulse circuits are inexpensively produced and reliable in operation.

Claims (5)

1. A clock pulse circuit for providing local clock pulses for a plurality of large scale integrated circuits, each contained on respective ones of a plurality of integrated circuit chips, the clock pulse circuit comprising: master clock means for producing master clock pulses having leading edges occurring at a predetermined frequency; pulse producing means for each of said integrated circuit chips, each pulse producing means being responsive to the leading edges of said master clock pulses for producing local clock pulses for the circuit on the respective integrated circuit chip, said local clock pulses being at said predetermined frequency and having pulse durations dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the respective integrated circuit chip and the environmental conditions to which the integrated circuit chip is subjected; and means connecting said master clock means to each of said pulse producing means.

2. A clock pulse circuit as claimed in claim 1 in which each pulse producing means includes a plurality of serially arranged delay circuits and a gate circuit, said serially arranged delay circuits being responsive to the leading edge of each master clock pulse to produce a respective delayed pulse having a leading edge, and said gate circuit being responsive to the leading edge of each master clock pulse to produce the leading edge of said local clock pulse and being responsive to the leading edge of each delayed pulse to produce the trailing edge of said local clock pulse.

3. A data handling network comprising: a plurality of large scale integrated circuits, each contained on respective ones of a plurality of integrated circuit chips; and a clock pulse circuit for deriving local clock pulses for the circuits on each respective integrated circuit chip, the clock pulse circuit comprising master clock means for producing master clock pulses having leading edges occurring at a predetermined frequency, pulse producing means on each of said integrated circuit chips responsive to the leading edge of said master clock pulses for producing local clock pulses for the circuit on the respective integrated circuit chip, said local clock pulses being at said predetermined frequency and having pulse durations dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the respective integrated circuit chip and the environmental conditions to which the integrated circuit chip is subjected, and means connecting said master clock means to each of said pulse producing means.

4. A network as claimed in claim 3 in which each pulse producing means includes a plurality of serially arranged delay circuits and a gate circuit integral with the respective integrated circuit chip, said serially arranged delay circuit being responsive to the leading edge of each master clock pulse to produce the respective delay pulse having a leading edge, and said gate circuit being responsive to the leading edge of each master clock pulse to produce the leading edge of said local clock pulse and being responsive to the leading edge of each delayed pulse to produce the trailing edge of said local clock pulse.

5. A clock pulse circuit or data handling network substantially as herein described with reference to and as shown in the accompanying drawings.