GB1560197A - Data transmission system - Google Patents

Description

(54) DATA TRANSMISSION SYSTEM (71) We N.V. PHILIPS' GLOEILAM PENFABRIEKEN, a limited liability Company, organised and established under the laws of the Kingdom of the Netherlands, of Emmasingel 29, Eindhoven, the Netherlands do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The invention relates to a data transmission system, comprising a data source having a data line connected to an output thereof, said data line having a plurality of interface units included in succession therein for coupling corresponding peripheral units to the data line, each said interface unit having a first input for a validation signal derived from the data source, a plurality of second inputs for further signals derived from the data source, a first output for applying a validation signal to the next interface unit of the succession (if present), and a second output corresponding to each said input for applying further output signals to the next interface unit of the succession (if present).

Such data transmission systems may, for example, form part of electronic computing systems. In such systems a central processing unit (CPU) is coupled to a plurality of peripheral units via a multiple line, the DATA bus, to which said peripheral units are connected via the interface units included in succession in the line. Such a configuration is generally referred to as a "daisy chain". Signals destined for the last peripheral unit of the chain have to pass through all the interface units, in each of which the signals pass in parallel through a plurality of circuit elements. These circuit elements may for example, perform an amplifier function and restore distorted signals to squarewave pulses.

The said circuit elements each give rise to a certain delay in the signal propagation, which delay may be different for the different data bus lines, with the result that normally simultaneous signals may appear at a given peripheral unit at different instants.

The signals should be utilized in each peripheral unit only when they are all present and when possible transient effects have decayed. In order to signal when this is so a validation signal, for example a clock signal, is also applied to the peripheral unit, the attainment of a specific value by said signal indicating that the signals on the other lines are valid. This validation signal is generated by the CPU, for example after a certain delay.

In known systems the tolerances in the various interface units may exhibit such a spread that the validation signal may have been subjected to only a small delay compared with the signals on the other lines after said signals have passed through several interface units, with the result that the validation signal arrives at a peripheral unit late in the chain prior to one or more of the other signals. It is of course possible to prevent this happening by increasing the time delay between the generation of the data signals by the CPU and the generation of the validation signal thereby. However, this has the drawback of giving rise to a substantially reduced data transmission speed. In this respect it should be noted that said time delay would generally be a fixed parameter, whereas the transit times of the various signals depend on various factors, such as the number of interface units in the chain (which number may vary), the spread among the various circuit elements etc. Thus it may even be the case that the line which carries the validation signal in a specific sample of the system may be the one which gives rise to the greatest delay. It is an object of the invention to mitigate this disadvantage, and in certain cases to allow the validation signal to even be generated by the CPU simultaneously with the other signals, if desired.

The invention provides a data transmission system, comprising a data source having a data line connected to an output thereof, said data line having a plurality of interface units included in succession therein for coupling corresponding peripheral units to the data line, each said interface unit having a first input for a validation signal derived from the data source, a plurality of second inputs for further signals derived from the data source, a first output for applying a validation signal to the next interface unit of the succession (if present), and a second output corresponding to each said second input for applying further output signals to the next interface unit of the succession (if present), characterized in that in all said interface units each said second input is conected to the corresponding second output by means of an individual similar cascade combination of given logic elements, in that each of said given logic elements is integrated in a semiconductor chip which also has a further logic element identical thereto integrated thereon, in that a set of said given logic elements formed by a corresponding said given logic element from each said cascade combination is distributed between at least two semiconductor chips, in that the further logic elements which correspond to the logic elements of each given said cascade combination are themselves interconnected to form a further such similar cascade combination, and that in that each of said further cascade combinations is included in a coupling between said validation signal input and said validation signal output in such manner that the application of a validation signal to said validation signal input in operation will result in the appearance of a validation signal at said validation signal output only after the outputs of all said further cascade combinations have responded to the input validation signal.

It has now been recognized that the fact that circuit elements which are incorporated in a single integrated semiconductor circuit normally exhibit only a small spread in parameters relative to each other can be used to ensure that the validation signal is delayed in each interface unit by at least the same amount as, but not significantly more than, the signals which are there subjected to the maximum delay.

An embodiment of the invention will be described, by way of example, with reference to the accompanying diagrammatic drawings in which Figure 1 shows part of a data transmission system, Figure 2 shows the construction of part of the system of Figure 1 and Figure 3 shows a time diagram illustrating the operation of the construction of Figure 2.

In the data transmission system of Figure 1 a central processing unit (CPU) 1, for example a computer of the Philips P300 or P400 series, is connected to a first further unit 3 via a multiple line 2 and thence to a second further unit 8 via a multiple line 7, and thence to one or more further units via a multiple line 12. Data signals, destination control signals and a clock signal are carried by the line 2. Transmission is possible in both directions and the line 2 therefore consists of two (multiple) sub-lines, which are each active in a different one of the two directions, or is a bi-directional bus line, or consists of some channels which are active in one direction and other channels which are active in both directions.

The further units 3 and 8 include interface units 4 and 9 respectively and processing units 5 and 10 respectively. The interface units 4 and 9 each include a separate circuit for each direction of transmission but, for the sake of simplicity the system will be described hereinafter for a single direction of transmission only. The peripheral units 5, 10 may each comprise a processing unit, for example a magnetic disc store of the Philips P3433 type, or a fast printer of the Philips P3310 type, or another processing unit of the relevant product series.

The interface unit 4 transfers the signals which are obtained from the central processing unit 1 to the processing unit 5, which processes them if they are destined for that processing unit. Signals not so destined are transferred to the next further unit 8 via the multiple line 7 under the control of a signal on the line 6. The signals which so arrive at unit 8 are applied to the processing unit 10 which processes them if they are destined therefor; otherwise they are transferred to the next further unit (not shown) via the interface unit 9 under control of a signal on line 11.

Figure 2 shows a possible construction for each of the interface units 4 and 9 of Figure 1. Each interface unit comprises six integrated circuits 60 to 65 of which functional units 40-49, 140-141, 50-59, 150, 151 are shown separately. The single inputs 20-29 form, for example, part of the line 2 in Figure 1, and are each connected to the input of a corresponding regeneration amplifier 40-49, which for example takes the form of a Schmitt trigger. Inputs 20-28 are for data and destination control signals and input 29 is for a validation signal. Two further regeneration amplifiers 140, 141 of a corresponding type are also provided, the inputs of these being connected in parallel with the output of amplifier 49. The integrated circuit 60 thus comprises four identical regeneration amplifiers 40, 41, 42. 140, and the same applies to each of the integrated circuits 62, 64. They may each in fact be formed by a module of the Signetics MC 1489 type. (Of course the number of regeneration amplifiers provided in each integrated circuit 60, 62, 64 will depend in practice on the particular system in which they are incorporated.) Signals which can be processed in the relevant processing unit 5 or 10 of Figure 1 appear on the outputs 80-89 of the regeneration amplifiers 40-49, these outputs being connected to the input of the relevant processing unit in a manner not shown. The appearance of a signal on output 89 indicates that the signals on the outputs 80-88 are valid. The signal appearing on output 89 may be used, for example, as a clock signal to activate the storage of the signals then appearing on the outputs 80-88 in a register of the processing unit 5, or to synchronize other processing operations, provided that said signals are destined for the relevant processing unit.

The outputs of the regeneration amplifier 40-49, 140, 141 are connected to first inputs of AND-gates 50-59, 150, 151 respectively.

The integrated circuit 61 comprises four suitably identical such AND-gates, as do each of the integrated circuits 63 and 65.

Each of these integrated circuits may take the form of a module of the Signetics MC 1488 type. In practice of course the number of AND-gates required per integrated circuit 61, 63, 65 will be determined by the particular environment in which the system is used. The AND-gates 50-58 each have their second input connected to a line 66.

This line corresponds, for example, to the line 6 in Figure 1. A signal on said line can thus control the transfer of the received input signals (lines 20-28) to the respective outputs (lines 70-78. The lines 70-79 correspond for example to the multiple line 7 in Figure 1. The presence of the line 66 permits the relevant peripheral unit to control the further passage of the signals along the multiple line 2-7-12 of Figure 1. Inputs 90, 91 are supplied with a logic 'X1" signal continuously, so that the gates 150, 151 are always enabled. The outputs of the gates 150, 151 are interconnected and d.c. coupled to the second input of gate 59. The line 68 functions as a so-called "wired ANDgate": the signal on line 68 is a logic "1" only if all the gates connected to it (i.e. 150, 151 in the present example) produce a logic "1" signal. This means that a transition from "0" to "1" on this line is not affected until the gate which is connected to it and which is subject to the greatest delay produces this "0-1" transition. This delay is determined by the construction of the corresponding gate and by the elements, such as the regeneration amplifiers 140, 141 in the present example, which are connected in the input thereto.

As an alternative AND-gate 59 may have three inputs to which the output signals of the elements 49, 150 and 151 respectively are applied. As a further alternative the "wired-AND" gate may be replaced by a "wired OR" gate whose output signal does not become "0" until the signal which arrives last exhibits a "1-0" transition. As a further alternative the "wired AND" gate may be replaced by a gate giving another logic function, e.g. NAND or NOR. Sometimes it may be useful to employ inverting circuit elements instead of the non-inverting elements shown.

The operation of the circuit arrangement of Figure 2 is illustrated in the time diagram of Figure 3. The reference numerals on the left of Figure 3 denote the correspondingly numbered points in the circuit of Figure 2.

The bottom line of the Figure is the time axis. It is assumed that a signal appears on all lines 20-29 at an instant te. This signal need not be a 0-1 transition for all lines 20-28, it may also be a signal transition in the other sense, or a signal involving no transition. The signal on line 20 passes through circuit element 40 in the integrated circuit 60 and circuit element 50 in integrated circuit 61. Subsequently, it appears on output 70 after a delay of t60 + t61, which delay depends on the properties of the relevant integrated circuits and is the same as the total delays occurring in the elements 41 and 51 (output 71), the elements 42 and 52 (output 72), and the elements 140 and 150. The equality of the various total delays arises because all the gates of each of the integrated circuits 60 and 61 have been manufactured by the same process at the same time in the same semiconductor body and thus have the same physical properties.

These physical properties moreover have the same temperature dependence.

In a similar way the signal on input 23 passes through the circuit element 43 in integrated circuit 62 and then through circuit element 53 in integrated circuit 63. The total delay before this signal appears at output 73 is t62 + t63. In the present example this delay (which is equal to the total delay in the elements 44 and 54 (output 74), in the elements 45 and 55 (output 75), and in the elements 141 and 151 for the reasons set out above) is greater than that at output 70.

In a similar way the signal on input 26 passes through circuit element 46 in integrated circuit 64 and circuit element 56 in integrated circuit 65. The total time delay before this signal appears at output 76 is t64 + t65. In the present example this delay (whish is equal to the total delay in the elements 47 and 57 (output 77), in the elements 48 and 58 (output 78) and in the elements 149 and 59)) is smaller than that at output 70.

In the present example the (validation) signal on input 29 is a "0-1" transition. This signal passes through circuit element 49 in semiconductor circuit 64 and thus appears on line 67 with a delay of t64. This signal is applied, inter alia, directly to one input of AND-gate 59 the other input of which is being initially fed with a "0"-signal, so that the output 79 remains at logic "0" for the time being. In addition, the signal on line 67 passes through the integrated circuits 60 + 61 and through the integrated circuits 62 + 63 in parallel. The resulting 0-1 transition on line 68 does not appear until the longest delay occurring in these two groups of circuits (in the present instance t62 + t63) has elapsed and it is not until then that the two inputs of the AND-gate 59 both receive a logic "l"-signal. When this occurs a "1"signal results on the output 79 after a further delay of t65 (the delay occurring in the integrated circuit 65.) This occurs at time ta, which is later than the instants at which the other signals appear on the respective outputs 70-78, i.e the delay at terminal 79 is longer than the longest total delay t62 + t63 otherwise occuring. Thus the validation or clock signal is prevented from occuring on output 79 before all the signals are present on the other output lines 70-78 and the turn-on transients therein have decayed.

It will be evident that the circuit arrangement of Figure 2 is only one of many possible such arrangements. For example, additional integrated circuits may be included between the integrated circuits 60. 62, 64 and the integrated circuits 61, 63, 65, in which case it must be arranged that a signal derived from the validation or clock signal is passed through each of these circuits in the same way as described for the circuits 60-63.

As a first alternative the outputs of all the gates 150, 151 and 59 may be d.c. coupled to each other in such manner as to give a wired-OR function, provided that the validation signal applied to input 29 is a 1-0 transistion. This can speed up the transit of the signals, because the additional delay t65 on the line 79 of Figure 3 will then be eliminated, while still ensuring that the signal on output 79 does not appear prematurely. As a second alternative the input validation signal on input 29 may be applied directly to the inputs of the regeneration amplifiers 140, 141. 49 in parallel (then omitting the coupling from the output of amplifier 49 to the inputs of amplifiers 140 and 141). The total delay occurring at output 79 will then be reduced by the amount of the delay t64 while still ensuring that the output signal does not appear at terminal 79 prematurely.

These two alternatives may even be used together, if desired. However, it is found that the set-up shown in the Figure provides greater reliability.

The circuit arrangement of Figure 2 may be modified by removing the connection shown between line 68 and the upper input of gate 59, connecting this upper input to terminal 90, and replacing the wired ANDfunction denoted by the line 68 by a wired AND-function between the outputs of gates 151 and 59, the upper input of gate 150 being transferred from terminal 90 to the output of this wired AND-function arrangement. Gate 150 will then produce the validation output signal.

Certain of the integrated circuits shown separately in Figure 2 may be formed by a single integrated circuit. For example the circuits 60 and 62 may be together formed by a single integrated circuit outputs of which feed two different integrated circuits as shown. If this is the case the single circuit may either comprise the two regeneration amplifiers 140, 141 shown, or only one of these. In the latter case its output will be connected both to the input of gate 150 and to the input of gate 151.

It will be appreciated that the delay occurring in integrated circuit 64 may be smaller than the maximum delay occurring in the integrated circuits 60 and 62, with the result that the validation signal for the corresponding processing unit may occur on terminal 89 before the signals on terminals 80-88 are valid. In general, however, the time difference will be so small that it will have no adverse effect, only the cumulative effect of such time differences occuring in several interface units in cascade producing a significant time difference, which cumulative effect is prevented by constructing the interface units in the manner shown. If the time difference between the signal at terminal 89 and the signals at the terminals 80-88 could cause problems the signal on output 79 may of course be used as the validation or clock signal for the corresponding processing unit.

WHAT WE CLAIM IS 1. A data transmission system, comprising a data source having a data line connected to an output thereof, said data line having a plurality of interface units included in succession therein for coupling corresponding peripheral units to the data line, each said interface unit having a first input for a validation signal derived from the data source, a plurality of second inputs for further signals derived from the data source.

a first output for applying a validation signal to the next interface unit of the succession (if present), and a second output corresponding to each said second input for applying further output signals to the next interface unit of the succession (if present) characterized in that in all said interface

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. output 70. In the present example the (validation) signal on input 29 is a "0-1" transition. This signal passes through circuit element 49 in semiconductor circuit 64 and thus appears on line 67 with a delay of t64. This signal is applied, inter alia, directly to one input of AND-gate 59 the other input of which is being initially fed with a "0"-signal, so that the output 79 remains at logic "0" for the time being. In addition, the signal on line 67 passes through the integrated circuits 60 + 61 and through the integrated circuits 62 + 63 in parallel. The resulting 0-1 transition on line 68 does not appear until the longest delay occurring in these two groups of circuits (in the present instance t62 + t63) has elapsed and it is not until then that the two inputs of the AND-gate 59 both receive a logic "l"-signal. When this occurs a "1"signal results on the output 79 after a further delay of t65 (the delay occurring in the integrated circuit 65.) This occurs at time ta, which is later than the instants at which the other signals appear on the respective outputs 70-78, i.e the delay at terminal 79 is longer than the longest total delay t62 + t63 otherwise occuring. Thus the validation or clock signal is prevented from occuring on output 79 before all the signals are present on the other output lines 70-78 and the turn-on transients therein have decayed. It will be evident that the circuit arrangement of Figure 2 is only one of many possible such arrangements. For example, additional integrated circuits may be included between the integrated circuits 60. 62, 64 and the integrated circuits 61, 63, 65, in which case it must be arranged that a signal derived from the validation or clock signal is passed through each of these circuits in the same way as described for the circuits 60-63. As a first alternative the outputs of all the gates 150, 151 and 59 may be d.c. coupled to each other in such manner as to give a wired-OR function, provided that the validation signal applied to input 29 is a 1-0 transistion. This can speed up the transit of the signals, because the additional delay t65 on the line 79 of Figure 3 will then be eliminated, while still ensuring that the signal on output 79 does not appear prematurely. As a second alternative the input validation signal on input 29 may be applied directly to the inputs of the regeneration amplifiers 140, 141. 49 in parallel (then omitting the coupling from the output of amplifier 49 to the inputs of amplifiers 140 and 141). The total delay occurring at output 79 will then be reduced by the amount of the delay t64 while still ensuring that the output signal does not appear at terminal 79 prematurely. These two alternatives may even be used together, if desired. However, it is found that the set-up shown in the Figure provides greater reliability. The circuit arrangement of Figure 2 may be modified by removing the connection shown between line 68 and the upper input of gate 59, connecting this upper input to terminal 90, and replacing the wired ANDfunction denoted by the line 68 by a wired AND-function between the outputs of gates 151 and 59, the upper input of gate 150 being transferred from terminal 90 to the output of this wired AND-function arrangement. Gate 150 will then produce the validation output signal. Certain of the integrated circuits shown separately in Figure 2 may be formed by a single integrated circuit. For example the circuits 60 and 62 may be together formed by a single integrated circuit outputs of which feed two different integrated circuits as shown. If this is the case the single circuit may either comprise the two regeneration amplifiers 140, 141 shown, or only one of these. In the latter case its output will be connected both to the input of gate 150 and to the input of gate 151. It will be appreciated that the delay occurring in integrated circuit 64 may be smaller than the maximum delay occurring in the integrated circuits 60 and 62, with the result that the validation signal for the corresponding processing unit may occur on terminal 89 before the signals on terminals 80-88 are valid. In general, however, the time difference will be so small that it will have no adverse effect, only the cumulative effect of such time differences occuring in several interface units in cascade producing a significant time difference, which cumulative effect is prevented by constructing the interface units in the manner shown. If the time difference between the signal at terminal 89 and the signals at the terminals 80-88 could cause problems the signal on output 79 may of course be used as the validation or clock signal for the corresponding processing unit. WHAT WE CLAIM IS

1. A data transmission system, comprising a data source having a data line connected to an output thereof, said data line having a plurality of interface units included in succession therein for coupling corresponding peripheral units to the data line, each said interface unit having a first input for a validation signal derived from the data source, a plurality of second inputs for further signals derived from the data source.

a first output for applying a validation signal to the next interface unit of the succession (if present), and a second output corresponding to each said second input for applying further output signals to the next interface unit of the succession (if present) characterized in that in all said interface

units each said second input is connected to the corresponding second output by means of an individual similar cascade combination of given logic elements, in that each of said given logic elements is integrated in a semiconductor chip which also has a further logic element identical thereto integrated thereon, in that a set of said given logic elements formed by a corresponding said given logic element from each said cascade combination is distributed between at least two semiconductor chips, in that the further logic elements which correspond to the logic elements of each given said cascade combination are themselves interconnected to form a further such similar cascade combination, and in that each of said further cascade combinations is included in a coupling between said validation signal input and said validation signal output in such manner that the application of a validation signal to said validation signal input in operation will result in the appearance of a validation signal at said validation signal output after the output of all said further cascade combinations have responded to the input validation signal.

2. A system as claimed in Claim 1, characterized in that each of said cascade combinations comprises a non-inverting transfer circuit as its input circuit and in that the validation signal input is coupled to the inputs of all said further cascade combinations except one via the non-inverting transfer circuit of the remaining said further cascade combination.

3. A system as claimed in Claim 2, characterized in that said non-inverting transfer circuits are regeneration amplifiers.

4. A system as claimed in Claim 1, 2 or 3 characterized in that each of said cascade combinations comprises a correspondence detector as its output circuit in that the correspondence detectors of all said further cascade combinations except one are connected to a correspondence circuit, and in that the output of said correspondence circuit is coupled to the validation signal output via the correspondence detector of the remaining said further cascade combination.

5. A system as claimed in Claim 4, characterized in that said correspondence circuit is a wired logic circuit.

6. A system as claimed in Claim 4 or Claim 5, characterized in that the correspondence detectors are logic AND-gates.

7. A data transmission system substantially as described herein with reference to Figures 1 and 2 of the drawings.