CA1094691A - Data transmission system - Google Patents
Data transmission systemInfo
- Publication number
- CA1094691A CA1094691A CA301,578A CA301578A CA1094691A CA 1094691 A CA1094691 A CA 1094691A CA 301578 A CA301578 A CA 301578A CA 1094691 A CA1094691 A CA 1094691A
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- Canada
- Prior art keywords
- circuit
- output
- signal
- logic
- series connections
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-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Information Transfer Systems (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PHD.77-029 ABSTRACT:
In electronic computer systems peripheral units are generally connected in series to the central processing unit via a common data bus. Via the data bus the data signals of one specific sign and, as the case may be, control signals are each time trans-mitted with a parallel clock signal, whose instant of appearance indicates when the other signals are valid.
All signals in each peripheral unit pass through the same number of circuit elements, in particular regene-ration amplifiers and logic circuits, a plurality of circuit elements being each time combined in one inte-grated semiconductor circuit, which may exhibit diffe-rent propagation delays. In order to ensure that also in a longer chain of peripheral units the clock sig-nal neither appears before the data signal with the greatest delay nor unnecessarily later so as to obtain the maximum transmission speed, the clock signal in each peripheral unit is in addition passed in parallel through all integrated semiconductor circuits and at the output of said circuits combined in such a way that the active state does not appear prior to said state at the output of the semiconductor circuit, or semiconductor circuits, with the greatest delay. Thus, the clock signal is always delayed to at least the same extent as the data signal with the greatest delay, for which some additional circuit elements must be included in each peripheral unit.
In electronic computer systems peripheral units are generally connected in series to the central processing unit via a common data bus. Via the data bus the data signals of one specific sign and, as the case may be, control signals are each time trans-mitted with a parallel clock signal, whose instant of appearance indicates when the other signals are valid.
All signals in each peripheral unit pass through the same number of circuit elements, in particular regene-ration amplifiers and logic circuits, a plurality of circuit elements being each time combined in one inte-grated semiconductor circuit, which may exhibit diffe-rent propagation delays. In order to ensure that also in a longer chain of peripheral units the clock sig-nal neither appears before the data signal with the greatest delay nor unnecessarily later so as to obtain the maximum transmission speed, the clock signal in each peripheral unit is in addition passed in parallel through all integrated semiconductor circuits and at the output of said circuits combined in such a way that the active state does not appear prior to said state at the output of the semiconductor circuit, or semiconductor circuits, with the greatest delay. Thus, the clock signal is always delayed to at least the same extent as the data signal with the greatest delay, for which some additional circuit elements must be included in each peripheral unit.
Description
t~ ~ 16 2l~-2-1978 "Data transmissic,n system"
- The invention relates to a data transmission system, comprising an active device, a data line which is connected to an output thereof, and a plura-lity of interface units which are included in series in the data line, for the connection of one peripheral unit each to the data line, an interface unit being connected to the data line by means of a first input for a validation input signal, a predetermined first number of second inputs for further input signals, a first output for a validation output signal, and a predetermined second number of second outputs for further output signals.
; Such interface units are for example employed in electronic computing systems. In such systems a central processing unit CPU i6 connected to a plura-lity of peripheral units via a multiple line, the DATA bus, to which said peripheral units are connected in series. Such a configuration is generally referred to as "daisy chain". The signals destined for the last ~0 peripheral unit of the chain then have to pass through the interface units of all peripheral units. In each peripheral unit/interface unit the signals are passed in parallel through a plurality of circuit elements with for example an amplifier function, which restores distorted signals to squarewave pulses. ~Iowever, also ~-.
~'111).7~-029 10~4t;~ -2-1978 a peripheral unit May perform the function of an ac-tive device.
The said circuit elements each give rise to a certain delay in the signal propagation3 which delay may differ among the respective data bus lines. The transition from the quiescent to the signal state (from an electrical point of view this may even mean an unchanged state) appears at the various peripheral units at different instants. In each peripheral unit lQ the signals should be utilized only when they all are present at the same instant and possible transient effects have decayed. In order to signal this a vali-dation signal, for example a clock signal, is also applied to the peripheral unit. A specific value of said signal then indicates that the signals on the other lines are valid. This validation signal may be generated by the active device, for example with a certain time delay.
During passage through a chain of peripheral units each with an interface unit the tolerances may exhibit such a spread that the validation signal passes through a line with a comparatively small delay. The validation signal would then arrive at the end of the chain of peripheral units prior to one or more other signals which pass through lines with a greater delay. The time delay before the generation of the validation signal by the active device can then be '' ~ ~ P~ )29 dimensioned so that said signal cannot appear prema-turely. This has the drawback of a substantially re-duced data transmission speed. In this respect it is to be noted that said delay time would generally be a fixed parameter. The transit time depends on various factors, such as the number of peripheral units in the chain (which number may vary), the spread among the various circuit elements, etc. Thus, under cer-tain conditions, the very line for the validation signal in a specific sample of the system may exhibit the greatest time delay.
It is an object of the invention to provide means which ensure that the validation signal does not appear prematurely. It is another object of the invention to realize this even if the validation sig~
nal is generated simultaneously with the other sig-nals. It is a further object of the invention to closely approximate the maximum transmission speed on the respective lines as, the validation signal not being rendered active until the other signals no longer exhibit any transient effects. According to the in-vention these objects are achieved in that all said second outputs are each connected to a corresponding input of said second inputs by means of an identical first seri~s connection o~ a third number of logic elements, -that all logic elements of at least one corresponding rank within said respective first 1'lll1.77-02
- The invention relates to a data transmission system, comprising an active device, a data line which is connected to an output thereof, and a plura-lity of interface units which are included in series in the data line, for the connection of one peripheral unit each to the data line, an interface unit being connected to the data line by means of a first input for a validation input signal, a predetermined first number of second inputs for further input signals, a first output for a validation output signal, and a predetermined second number of second outputs for further output signals.
; Such interface units are for example employed in electronic computing systems. In such systems a central processing unit CPU i6 connected to a plura-lity of peripheral units via a multiple line, the DATA bus, to which said peripheral units are connected in series. Such a configuration is generally referred to as "daisy chain". The signals destined for the last ~0 peripheral unit of the chain then have to pass through the interface units of all peripheral units. In each peripheral unit/interface unit the signals are passed in parallel through a plurality of circuit elements with for example an amplifier function, which restores distorted signals to squarewave pulses. ~Iowever, also ~-.
~'111).7~-029 10~4t;~ -2-1978 a peripheral unit May perform the function of an ac-tive device.
The said circuit elements each give rise to a certain delay in the signal propagation3 which delay may differ among the respective data bus lines. The transition from the quiescent to the signal state (from an electrical point of view this may even mean an unchanged state) appears at the various peripheral units at different instants. In each peripheral unit lQ the signals should be utilized only when they all are present at the same instant and possible transient effects have decayed. In order to signal this a vali-dation signal, for example a clock signal, is also applied to the peripheral unit. A specific value of said signal then indicates that the signals on the other lines are valid. This validation signal may be generated by the active device, for example with a certain time delay.
During passage through a chain of peripheral units each with an interface unit the tolerances may exhibit such a spread that the validation signal passes through a line with a comparatively small delay. The validation signal would then arrive at the end of the chain of peripheral units prior to one or more other signals which pass through lines with a greater delay. The time delay before the generation of the validation signal by the active device can then be '' ~ ~ P~ )29 dimensioned so that said signal cannot appear prema-turely. This has the drawback of a substantially re-duced data transmission speed. In this respect it is to be noted that said delay time would generally be a fixed parameter. The transit time depends on various factors, such as the number of peripheral units in the chain (which number may vary), the spread among the various circuit elements, etc. Thus, under cer-tain conditions, the very line for the validation signal in a specific sample of the system may exhibit the greatest time delay.
It is an object of the invention to provide means which ensure that the validation signal does not appear prematurely. It is another object of the invention to realize this even if the validation sig~
nal is generated simultaneously with the other sig-nals. It is a further object of the invention to closely approximate the maximum transmission speed on the respective lines as, the validation signal not being rendered active until the other signals no longer exhibit any transient effects. According to the in-vention these objects are achieved in that all said second outputs are each connected to a corresponding input of said second inputs by means of an identical first seri~s connection o~ a third number of logic elements, -that all logic elements of at least one corresponding rank within said respective first 1'lll1.77-02
2~-2- 1 9''~f~
.~0~ 3~
series connections are arranged in at least two groups which together include all logic elements of said rank and thus include fourth numbers of mutually identical logic circuits, which each belong to a different one of said first series connections, plus at least one further additional logic circuit which is identical thereto, all logic circuits of a group thus formed, including said associated at least one additional logic circuit, together constituting one integrated semiconductor circuit, that each additional logic circuit is included in a second series connec-tion of logic elements between a third input and a third output, the first and second series connections being identical to each other, and that all third inputs are connected so as to receive said validation input signal and that all third outputs are connected so as to generate said validation output signal only in the case of correspondence o-f their output signals after receipt of said validation input signal. The aforementioned steps are mainly based on the recog-nition that circuit elements which are incorporated in a single integrated semiconductor circuit exhibit a minimal spread in parameters relative to each other. In each interface unit the validation signal is then deLayed by at least the same amount as, but no$ significantly more than, the signals which aLre there subjected to thLe maximum delay. Thus, also in l'l~l).77-029
.~0~ 3~
series connections are arranged in at least two groups which together include all logic elements of said rank and thus include fourth numbers of mutually identical logic circuits, which each belong to a different one of said first series connections, plus at least one further additional logic circuit which is identical thereto, all logic circuits of a group thus formed, including said associated at least one additional logic circuit, together constituting one integrated semiconductor circuit, that each additional logic circuit is included in a second series connec-tion of logic elements between a third input and a third output, the first and second series connections being identical to each other, and that all third inputs are connected so as to receive said validation input signal and that all third outputs are connected so as to generate said validation output signal only in the case of correspondence o-f their output signals after receipt of said validation input signal. The aforementioned steps are mainly based on the recog-nition that circuit elements which are incorporated in a single integrated semiconductor circuit exhibit a minimal spread in parameters relative to each other. In each interface unit the validation signal is then deLayed by at least the same amount as, but no$ significantly more than, the signals which aLre there subjected to thLe maximum delay. Thus, also in l'l~l).77-029
3~;g l ~8-2 l~78 a long chain of interface units, the validation signal appears briefly after the turn-on transient of the signal with the greatest delay, independently of the spread in tolerances.
Suitably said series connections comprise a non-inverting transfer circuit as input circuit and the validation input signal is applied to the third inputs of the remaining second series connections via the non-inverting transfer circuit of a predeter-mined first one of said second series connections.
The non-inverting transfer circuits are for example regeneration amplifiers. The input signals are sorne-times appreciably distorted owing to the line capa-citances and other effects. Such regeneration ampli-fiers then ensure that the signals are restored to suitable square-wave pulses. In order to reduce the load presented to the validation signal on the one line and in order to provide a certain additional precaution in respect of the delay of the validation signal this is once again additionally delayed by a time which corresponds to the delay time in such a non-inverting transfer circuit.
Suitably said series connections comprise a correspondence detector as output circuits, the correspondence detector of a predetermined first one o~ said second series connections supplies said validation output signal, and the third outputs of -G-7~ 9 ` 10~3~ 2~-2-1978 . . . . .
the remaining second series connections in a corres-pondence circuit are connected to an input of the correspondence detector of said first one of said second series connections. Thus, the correspondence detector (for example a logic AND-gate) is employed to provide an additional delay so as to further in-crease the safety margin.
Suitably said correspondence circuit performs a wired logic function. This is a reliable and inex-pensive set~up.
The invention will be described in more detail with reference to some Figures. Fig. 1 schema-tically represents the circuit arrangement of a part of the complete system. Fig. 2 schematically repre-sents the circuit arrangement of an interface unit.
Fig. 3 shows a time diagram of the signals, In Fig. 1 the central processing unit ~CPU)1 `~
is a computer of the Philips P300 or P400 series, which via a multiple line 2 is connected to the peri-pheral unit 3. The peripheral units 3, ~ are for example a magnetic disc store of the Philips P3433 type or a fast printer of the Philips P3310 type.
It is also possible to employ other peripheral units of the relevant product series. Data control signals and a clock signal are conveyed via the line 2. Trans-mission should be possible in both directions and for this purpose the line 2 either consists of two --7~
2g_z_l~78 3~ .
multiple sub-li.nes, which are each active in one of the two directions, or it is a bi-directional bus line. Furthermore, some connections of the line 2 may be active in one direction and other connections in two directions. In both cases the steps in accor-dance with the invention may be utilized. The inter-face unit 4 may then include a separate circuit as is to be described hereinafter, for each direction of transmission. For the sake of simplicity the de-vice is described hereinafter, for a single direction of transmission only.
The peripheral unit 3 compr:ises an interface unit 4 and a processing unit 5. The invention does not relate to the functions of the processing unit.
In the interface unit 4 the signals which are ob-tained from the central processing unit 1 and which are destined for the peripheral unit 3 are trans-ferred to the processing unit 5. This is then con-trolled by signals on the line 6, which for the sake of brevity are not described in any more detail. In the opposite case the appli.ed signals are not led to the processing unit 5, or processed therein, but are transferred to the ne~t peripheral unit 8 under con-trol of a signal on the line 6, via the multiple line 7. Under control of a signal on line 11 the sig-nals which have arrived are appli.ed to either the processing element 10 or to a further peripheral unit, B
. -- .
~ fi~i PHD 77-029 not shown, via the interface unit 9.
Fig. 2 gives an example of the circuit ar-rangement of an interface unit such as the units 4, 9 in Fig. 1. In the present example the device com-prises six integrated circuits 60 to 65 of which the functional units 40-49, 140, 141, 50-59, 150, 151 are shown separately. The lines/inputs 20-29 are singular and for example form part of the line 2 in Fig. 1. They are each connected to the input of the corresponding regeneration amplifier 40-49, which for example takes the form of a Schmitt trigger.
Furthermore, there are provided two further regene-ration amplifiers 140, 141 of a corresponding type whose inputs are connected in parallel with the output of amplifier 49. The integrated circuit 60 thus com-prisès four identical regeneration amplifiers 40, 41, 42, 140. The same applies to each of the integrated circuits 62, 64. They may be realized by a module of the type Signetics MC 1489. In principle the number of regeneration amplifiers per integrated circuit (60, 62, 64) is arbitrary. On the outputs 80-89 of the regeneration amplifiers 40-49 signals are available for processing in the relevant processing unit, such as the units 5, 10 in Fig. 1. The appear-ance of the signal on oul:put 89 indicates that the - signals on the outputs 8()-88 are valid and in a device in accordance with the invention it is then _ g _ PIID.77~029 2S~2-1'378 ~O~
ensured that they have the correct values. The clock signal on output 89 may then for example activate the storage of the other signals on the outputs 80-88 in a register of the processing unit 5, or in a diffe-rent manner start or synchronize further processing operations, provided that said signals are destined for the relevant peripheral unit. This destination may be controlled by a signal on the relevant line of the, as the case may be, multiple line of lines 6, 11. This further transfer, and further processing of the signals in the relevant peripheral unit is not discussed in any more detail.
The outputs of the- regeneration amplifiers 40-~lg, 140, 141 are respectively connected to one input of the AND-gates 50-59, 150, 151. The integrated circui-t 61 comprises four of such mutually identical ~ND-gates. On the other hand, the integrated circuit 63, 65 also comprises four mutually identical AND-gates. They may each be realized by a module of the type Signetics MC 1488. In principle the number of AND-gates per integrated circuit (61, 63, 65) is optional. The AND-gates 50-58 each have their second input connected to the line 66. This line thus cor-responds -to for example the line 6 in Fig. 1. A
signal on said line can thus control the tr~nsfer o~
the rcceived input s:ignals (lines 20-28) to the respective outputs (:Lines 70-78). Thus, the lines I"-ID . ~/'`j~()f'~) 28-2- 1 97~
~1)9~6~1 70-79 for example correspond to the mul-tiple l:ine 7 in Fig. 1. The signal on line 66 permits the relevant peripheral unit -to control the further passage of the signals along the multiple line (2-7-12). The inputs 90, 91 are continuously connected to a logic "1"
signal, so that the gates 150, 151 are always open.
The outputs of the gates 150, 151 are interconnected and are d.c. coupled to the second input of gate 59.
~wing to the described circuit arrangement of the gates in the integrated circuits 61, 63, 65 this is permissible. Specifically, it is thus ensured that the line 68 functions as a so called "wired AND-gate":
the signal on line 68 is a logic "1" only if all the gates connected to it (i.e. 150, 151 in the present example) supply a logic "1" signal. This means that during a transition from "O~ to "1" on this line this is not effected until the gate which is connected to it and which has the greatest delay produces this "0-1" transition. This delay is then further deter-mined by further elements such as the regeneration amplifiers 140, 141 in the present example, which are connected in series with said gate.
The "wired AND" function described is known per se and is not cxp]ained in more detail. In cer-tain cases AND-gate 59 may have three inputs to which the outpu1 signals Or the elements 49, 150 and 151 are then applied directly. Other constructions are PlID ~7_o~
~09~6'~ 2-1978 also possible, for example the use of a "wired OR"
gate whose output signal does not become "O" until the signal which arrives last exhibits the "1-0"
transition. Corresponding situations obtain when other logic functions (NAND, NOR) are ~ormed. Sometimes it may be useful to employ inverting circuit elements instead of the non-inverting elements shown.
The operation of the circuit arrangement in accordance with Fig. 2 is explained by means of the time diagram in Fig. 3. The re~erence numerals on the left relate to the correspondingly numbered elements of the circuit in accordance with Fig. 2.
The bottom line is the time axis. In the present example a signal appears on all lines 20-29 at the instant te. This need not be a 0-1 transition for all lines 20-28, it may also be a signal transition in the other sense, or a signal without signal tran-sition. The signal on line 20 passes through circuit element 40 in the semiconductor circuit 60 and circuit element 50 in semiconductor c~rcuit 61. Subsequently, it appears on output 70 with a delay t60 ~ t61 which delay depends on the properties of the semiconductor circuits and is equal to the delays in the respective series connections of the elements 41 and 51 (output 71'' elements 42 and 52 (output 72), and elements 140 and 150 wi~h a high degree of accuracy, because the semiconductor circuits 60 and 61 have been manufactured ' ~.
. -12- ~r ~, ~ PHD 77-029 integrally and thus have the same physical properties for each integrally manufactured circuit element. This also applies to the temperature dependence of the various properties.
In a similar way the signal on output 73 passes through the circuit element 43 in semiconduc-tor circuit 62 and circuit element 53 in semiconduc-tor circuit 63. The total delay time at output 73 is then t62 + t63. In the present example this delay time is greater than that at output 70 and is also highly equal to the delay times in the respective series connections of the elements 44 and 54 (output 74), elements 45 and 55 (output 75), and elements 141 and 151. In a similar way the signal on input 26 passes through circuit element 46 in semiconductor circuit 64 and circuit element 56 in semiconductor circuit 65. The total time delay at output 76 is then t64 + t65. In the present example this delay time is smaller than that at output 70 and is again sub-stantially equal to the delay times in the respective series connections of elements 47 and 57 (output 77), elements 48 and 58 (output 78), and elements 49 and 59.
In the present example the signal on input 29 is a "0-1" transition. This signal passes through circuit element 49 in semiconductor circuit 64 and thus appears on line 67 with a delay of t64. On the f~
~O.'~l~691 I'IIL) 77-029 ....
one hand this signal arrives directly at an input of AND-gate 59. For the time being this AND-gate is closed as a result of a "O"-signal which then appears on the other input. The output ~9 then remains a logic "O" for the time being. In addition, the signal on line 67 passes in parallel through the respective series-connected semiconductor circuits 60 + 61, 62 + 63. The 0-1 transition on line 68 does not appear until the maximum delay time (in the present instance t62 + t63) has elapsed. It is not until then that the two inputs of the AND-gate 59 receive a logic "1"-signal which appears on the output 79 after the delay t65 of the semiconductor circuit 65. On the time axis t this is designated ta. This instant appears definitely later than the instants at which the other signals appear on the respective outputs 70-78, i.e.
also later than the longest delay time t62 + t63 in this case. Thus, it is prevented in a reliable manner that the clock signal on output 79 appears prior to any of the signals on the other output lines.
The circuit arrangement of Fig. 2 has only been given by way of example. For example, between the integrated circuits 60, 62, 64 on the one hand and 61 63, 65 on the other hand additional circuits may be include~. Then it is merely necessary that always a signal derived from the clock pulse signal is a]so passed through these circuits in the same way as _ 1 l~_ Pl-ll),77-02~
lO~G'3~ 28-2-l97~3 described for the circuits 60-63. It is also possible that the outputs of the gates 150, 151 and 59 are d.c. coupled to each other so as to form a wired-OR
function. This ensures a faster transit of the sig-nals, because in this case the additional delay t65 on the last but one line of Fig. 3 is eliminated. The signal on output 79 then does not appear prematurely.
On the other hand it is also possible that the input signal on input 29 is directly applied in parallel to the inputs of the regeneration amplifiers 140, 141, Ll9. The total delay time at output 79 is then eliminated, i-e. the delay t64. In this case the output signal will neither appear prematurely, In specific cases the two last-mentioned steps may even be combined. IIowever, the set-up in accordance with the Figure provides greater reliabllit~. A
modification of the circuit arrangement in accordance with Fig. 2 is that between the outputs of gates 151 and 59 the AND-function is formed, that gate 59 is not connected to line 68 but to a continuous logic "1" signal, and that line 68 is connected to terminal 90, while gate 150 then supplies the valida-tion output signal. Furthermore~ it is possiblc that for e~ample the elemerlts 60 and 62 together con-stitute one integrated circuit which energizes two different integrated circuits. In that case this circuit should either comprise two additional re-~09~t-'31 2~J-2-1978 generation amplif,iers 140, 141 or only one regeneratiOn amplifier whose outpu-t is connected both to the input of gate 150 and that of gate 151 .
If the interface unit shown in Fig. 2 is connected directly to the OUtp11t of the central pro-cessing unit 1 in Fig. 1, it is possible that the delay time in integrated circuit 64 is smaller than the maximum delay time sustained in the integrated circuit 60, 62. Generally, this difference will be so small that it has no adverse ef`fect. The very problem solved by the invention occurs in the case of a series connection of a plurality of stations, be-cause then the worst case could become impermissible.
However, it is alternatively possible f`or this first station, as the case may be also for further stations, to use the signal on output 79 as cloc~ signal for the relevant processing unit.
Suitably said series connections comprise a non-inverting transfer circuit as input circuit and the validation input signal is applied to the third inputs of the remaining second series connections via the non-inverting transfer circuit of a predeter-mined first one of said second series connections.
The non-inverting transfer circuits are for example regeneration amplifiers. The input signals are sorne-times appreciably distorted owing to the line capa-citances and other effects. Such regeneration ampli-fiers then ensure that the signals are restored to suitable square-wave pulses. In order to reduce the load presented to the validation signal on the one line and in order to provide a certain additional precaution in respect of the delay of the validation signal this is once again additionally delayed by a time which corresponds to the delay time in such a non-inverting transfer circuit.
Suitably said series connections comprise a correspondence detector as output circuits, the correspondence detector of a predetermined first one o~ said second series connections supplies said validation output signal, and the third outputs of -G-7~ 9 ` 10~3~ 2~-2-1978 . . . . .
the remaining second series connections in a corres-pondence circuit are connected to an input of the correspondence detector of said first one of said second series connections. Thus, the correspondence detector (for example a logic AND-gate) is employed to provide an additional delay so as to further in-crease the safety margin.
Suitably said correspondence circuit performs a wired logic function. This is a reliable and inex-pensive set~up.
The invention will be described in more detail with reference to some Figures. Fig. 1 schema-tically represents the circuit arrangement of a part of the complete system. Fig. 2 schematically repre-sents the circuit arrangement of an interface unit.
Fig. 3 shows a time diagram of the signals, In Fig. 1 the central processing unit ~CPU)1 `~
is a computer of the Philips P300 or P400 series, which via a multiple line 2 is connected to the peri-pheral unit 3. The peripheral units 3, ~ are for example a magnetic disc store of the Philips P3433 type or a fast printer of the Philips P3310 type.
It is also possible to employ other peripheral units of the relevant product series. Data control signals and a clock signal are conveyed via the line 2. Trans-mission should be possible in both directions and for this purpose the line 2 either consists of two --7~
2g_z_l~78 3~ .
multiple sub-li.nes, which are each active in one of the two directions, or it is a bi-directional bus line. Furthermore, some connections of the line 2 may be active in one direction and other connections in two directions. In both cases the steps in accor-dance with the invention may be utilized. The inter-face unit 4 may then include a separate circuit as is to be described hereinafter, for each direction of transmission. For the sake of simplicity the de-vice is described hereinafter, for a single direction of transmission only.
The peripheral unit 3 compr:ises an interface unit 4 and a processing unit 5. The invention does not relate to the functions of the processing unit.
In the interface unit 4 the signals which are ob-tained from the central processing unit 1 and which are destined for the peripheral unit 3 are trans-ferred to the processing unit 5. This is then con-trolled by signals on the line 6, which for the sake of brevity are not described in any more detail. In the opposite case the appli.ed signals are not led to the processing unit 5, or processed therein, but are transferred to the ne~t peripheral unit 8 under con-trol of a signal on the line 6, via the multiple line 7. Under control of a signal on line 11 the sig-nals which have arrived are appli.ed to either the processing element 10 or to a further peripheral unit, B
. -- .
~ fi~i PHD 77-029 not shown, via the interface unit 9.
Fig. 2 gives an example of the circuit ar-rangement of an interface unit such as the units 4, 9 in Fig. 1. In the present example the device com-prises six integrated circuits 60 to 65 of which the functional units 40-49, 140, 141, 50-59, 150, 151 are shown separately. The lines/inputs 20-29 are singular and for example form part of the line 2 in Fig. 1. They are each connected to the input of the corresponding regeneration amplifier 40-49, which for example takes the form of a Schmitt trigger.
Furthermore, there are provided two further regene-ration amplifiers 140, 141 of a corresponding type whose inputs are connected in parallel with the output of amplifier 49. The integrated circuit 60 thus com-prisès four identical regeneration amplifiers 40, 41, 42, 140. The same applies to each of the integrated circuits 62, 64. They may be realized by a module of the type Signetics MC 1489. In principle the number of regeneration amplifiers per integrated circuit (60, 62, 64) is arbitrary. On the outputs 80-89 of the regeneration amplifiers 40-49 signals are available for processing in the relevant processing unit, such as the units 5, 10 in Fig. 1. The appear-ance of the signal on oul:put 89 indicates that the - signals on the outputs 8()-88 are valid and in a device in accordance with the invention it is then _ g _ PIID.77~029 2S~2-1'378 ~O~
ensured that they have the correct values. The clock signal on output 89 may then for example activate the storage of the other signals on the outputs 80-88 in a register of the processing unit 5, or in a diffe-rent manner start or synchronize further processing operations, provided that said signals are destined for the relevant peripheral unit. This destination may be controlled by a signal on the relevant line of the, as the case may be, multiple line of lines 6, 11. This further transfer, and further processing of the signals in the relevant peripheral unit is not discussed in any more detail.
The outputs of the- regeneration amplifiers 40-~lg, 140, 141 are respectively connected to one input of the AND-gates 50-59, 150, 151. The integrated circui-t 61 comprises four of such mutually identical ~ND-gates. On the other hand, the integrated circuit 63, 65 also comprises four mutually identical AND-gates. They may each be realized by a module of the type Signetics MC 1488. In principle the number of AND-gates per integrated circuit (61, 63, 65) is optional. The AND-gates 50-58 each have their second input connected to the line 66. This line thus cor-responds -to for example the line 6 in Fig. 1. A
signal on said line can thus control the tr~nsfer o~
the rcceived input s:ignals (lines 20-28) to the respective outputs (:Lines 70-78). Thus, the lines I"-ID . ~/'`j~()f'~) 28-2- 1 97~
~1)9~6~1 70-79 for example correspond to the mul-tiple l:ine 7 in Fig. 1. The signal on line 66 permits the relevant peripheral unit -to control the further passage of the signals along the multiple line (2-7-12). The inputs 90, 91 are continuously connected to a logic "1"
signal, so that the gates 150, 151 are always open.
The outputs of the gates 150, 151 are interconnected and are d.c. coupled to the second input of gate 59.
~wing to the described circuit arrangement of the gates in the integrated circuits 61, 63, 65 this is permissible. Specifically, it is thus ensured that the line 68 functions as a so called "wired AND-gate":
the signal on line 68 is a logic "1" only if all the gates connected to it (i.e. 150, 151 in the present example) supply a logic "1" signal. This means that during a transition from "O~ to "1" on this line this is not effected until the gate which is connected to it and which has the greatest delay produces this "0-1" transition. This delay is then further deter-mined by further elements such as the regeneration amplifiers 140, 141 in the present example, which are connected in series with said gate.
The "wired AND" function described is known per se and is not cxp]ained in more detail. In cer-tain cases AND-gate 59 may have three inputs to which the outpu1 signals Or the elements 49, 150 and 151 are then applied directly. Other constructions are PlID ~7_o~
~09~6'~ 2-1978 also possible, for example the use of a "wired OR"
gate whose output signal does not become "O" until the signal which arrives last exhibits the "1-0"
transition. Corresponding situations obtain when other logic functions (NAND, NOR) are ~ormed. Sometimes it may be useful to employ inverting circuit elements instead of the non-inverting elements shown.
The operation of the circuit arrangement in accordance with Fig. 2 is explained by means of the time diagram in Fig. 3. The re~erence numerals on the left relate to the correspondingly numbered elements of the circuit in accordance with Fig. 2.
The bottom line is the time axis. In the present example a signal appears on all lines 20-29 at the instant te. This need not be a 0-1 transition for all lines 20-28, it may also be a signal transition in the other sense, or a signal without signal tran-sition. The signal on line 20 passes through circuit element 40 in the semiconductor circuit 60 and circuit element 50 in semiconductor c~rcuit 61. Subsequently, it appears on output 70 with a delay t60 ~ t61 which delay depends on the properties of the semiconductor circuits and is equal to the delays in the respective series connections of the elements 41 and 51 (output 71'' elements 42 and 52 (output 72), and elements 140 and 150 wi~h a high degree of accuracy, because the semiconductor circuits 60 and 61 have been manufactured ' ~.
. -12- ~r ~, ~ PHD 77-029 integrally and thus have the same physical properties for each integrally manufactured circuit element. This also applies to the temperature dependence of the various properties.
In a similar way the signal on output 73 passes through the circuit element 43 in semiconduc-tor circuit 62 and circuit element 53 in semiconduc-tor circuit 63. The total delay time at output 73 is then t62 + t63. In the present example this delay time is greater than that at output 70 and is also highly equal to the delay times in the respective series connections of the elements 44 and 54 (output 74), elements 45 and 55 (output 75), and elements 141 and 151. In a similar way the signal on input 26 passes through circuit element 46 in semiconductor circuit 64 and circuit element 56 in semiconductor circuit 65. The total time delay at output 76 is then t64 + t65. In the present example this delay time is smaller than that at output 70 and is again sub-stantially equal to the delay times in the respective series connections of elements 47 and 57 (output 77), elements 48 and 58 (output 78), and elements 49 and 59.
In the present example the signal on input 29 is a "0-1" transition. This signal passes through circuit element 49 in semiconductor circuit 64 and thus appears on line 67 with a delay of t64. On the f~
~O.'~l~691 I'IIL) 77-029 ....
one hand this signal arrives directly at an input of AND-gate 59. For the time being this AND-gate is closed as a result of a "O"-signal which then appears on the other input. The output ~9 then remains a logic "O" for the time being. In addition, the signal on line 67 passes in parallel through the respective series-connected semiconductor circuits 60 + 61, 62 + 63. The 0-1 transition on line 68 does not appear until the maximum delay time (in the present instance t62 + t63) has elapsed. It is not until then that the two inputs of the AND-gate 59 receive a logic "1"-signal which appears on the output 79 after the delay t65 of the semiconductor circuit 65. On the time axis t this is designated ta. This instant appears definitely later than the instants at which the other signals appear on the respective outputs 70-78, i.e.
also later than the longest delay time t62 + t63 in this case. Thus, it is prevented in a reliable manner that the clock signal on output 79 appears prior to any of the signals on the other output lines.
The circuit arrangement of Fig. 2 has only been given by way of example. For example, between the integrated circuits 60, 62, 64 on the one hand and 61 63, 65 on the other hand additional circuits may be include~. Then it is merely necessary that always a signal derived from the clock pulse signal is a]so passed through these circuits in the same way as _ 1 l~_ Pl-ll),77-02~
lO~G'3~ 28-2-l97~3 described for the circuits 60-63. It is also possible that the outputs of the gates 150, 151 and 59 are d.c. coupled to each other so as to form a wired-OR
function. This ensures a faster transit of the sig-nals, because in this case the additional delay t65 on the last but one line of Fig. 3 is eliminated. The signal on output 79 then does not appear prematurely.
On the other hand it is also possible that the input signal on input 29 is directly applied in parallel to the inputs of the regeneration amplifiers 140, 141, Ll9. The total delay time at output 79 is then eliminated, i-e. the delay t64. In this case the output signal will neither appear prematurely, In specific cases the two last-mentioned steps may even be combined. IIowever, the set-up in accordance with the Figure provides greater reliabllit~. A
modification of the circuit arrangement in accordance with Fig. 2 is that between the outputs of gates 151 and 59 the AND-function is formed, that gate 59 is not connected to line 68 but to a continuous logic "1" signal, and that line 68 is connected to terminal 90, while gate 150 then supplies the valida-tion output signal. Furthermore~ it is possiblc that for e~ample the elemerlts 60 and 62 together con-stitute one integrated circuit which energizes two different integrated circuits. In that case this circuit should either comprise two additional re-~09~t-'31 2~J-2-1978 generation amplif,iers 140, 141 or only one regeneratiOn amplifier whose outpu-t is connected both to the input of gate 150 and that of gate 151 .
If the interface unit shown in Fig. 2 is connected directly to the OUtp11t of the central pro-cessing unit 1 in Fig. 1, it is possible that the delay time in integrated circuit 64 is smaller than the maximum delay time sustained in the integrated circuit 60, 62. Generally, this difference will be so small that it has no adverse ef`fect. The very problem solved by the invention occurs in the case of a series connection of a plurality of stations, be-cause then the worst case could become impermissible.
However, it is alternatively possible f`or this first station, as the case may be also for further stations, to use the signal on output 79 as cloc~ signal for the relevant processing unit.
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS
1. A data transmission system, comprising an active device, a data line which is connected to an output thereof, and a plurality of interface units which are included in series in the data line, for the connection of one peripheral unit each to the data line, an interface unit being connected to the data line by means of a first input for a validation input signal, a predetermined first number of second inputs for further input signals, a first output for a validation output signal, and a predetermined second number of second outputs for further output signals, characterized in that all said second outputs are each connected to a corresponding input of said second inputs by means of an identical first series connec-tion of a third number of logic elements, that all logic elements of at least one corresponding rank within said respective first series connections are arranged in at least two groups which together include all logic elements of said rank and thus include fourth numbers of mutually identical logic circuits which each belong to a different one of said first series connections, plus at least one further addi-tional logic circuit which is identical thereto, all logic circuits of a group thus formed, including said PHD.77-029 associated at least one additional logic circuit, together constituting one integrated semiconductor circuit, that each additional logic circuit is in-cluded in a second series connection of` logic elements between a third input and a third output, the first and second series connections being identical to each other, and that all third inputs are connected so as to receive said validation input signal and that all third outputs are connected so as to generate said validation output signal only in the case of correspondence of their output signals after receipt of said validation input signal.
2. A system as claimed in Claim 1, characterized in that said series connections comprise a non-in-verting transfer circuit as input circuit and the validation input signal is applied to the third in-puts of the remaining second series connections via the non-inverting transfer circuit of a predetermined first one of said second series connections.
3. A system as claimed in Claim 2, characterized in that said non-inverting transfer circuits are regeneration amplifiers.
4. A system as claimed in Claim 1, characterized in that said series connections comprise a correspon-dence detector as output circuits, the correspondence detector of a predetermined first one of said second series connections supplies said validation output PHD.77-029 signal, and the third outputs of the remaining second series connections in a correspondence circuit are connected to an input of the correspondence detector of said first one of said second series connections.
5. A system as claimed in Claim 4, characterized in that said correspondence circuit performs a wired logic function.
6. A system as claimed in Claim 4, characterized in that the correspondence detectors are logic AND-gates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2718473A DE2718473C3 (en) | 1977-04-26 | 1977-04-26 | Circuit arrangement for the parallel transmission of signals over several parallel lines |
| DE2718473.2 | 1977-04-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1094691A true CA1094691A (en) | 1981-01-27 |
Family
ID=6007286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA301,578A Expired CA1094691A (en) | 1977-04-26 | 1978-04-20 | Data transmission system |
Country Status (9)
| Country | Link |
|---|---|
| JP (1) | JPS53133341A (en) |
| BR (1) | BR7802532A (en) |
| CA (1) | CA1094691A (en) |
| DE (1) | DE2718473C3 (en) |
| FR (1) | FR2389285A1 (en) |
| GB (1) | GB1560197A (en) |
| IT (1) | IT1095211B (en) |
| NL (1) | NL7804376A (en) |
| SE (1) | SE426107B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2558320B1 (en) * | 1983-12-21 | 1986-04-18 | Philips Ind Commerciale | DEVICE FOR SERIAL CONNECTION OF A PLURALITY OF TRANSMITTING ELECTRONIC DEVICES |
| JPH0827705B2 (en) * | 1990-07-25 | 1996-03-21 | インターナショナル・ビジネス・マシーンズ・コーポレイション | adapter |
| DE19711997A1 (en) * | 1997-03-13 | 1998-09-17 | Francotyp Postalia Gmbh | Arrangement for communication between a base station and other stations of a mail processing machine and for their emergency shutdown |
| DE102004047345A1 (en) * | 2004-09-29 | 2006-02-16 | Siemens Ag | Computer control system for lighting installation in building has DALI gateway control system with plus and minus terminals connected to load current amplifier and lighting control units |
-
1977
- 1977-04-26 DE DE2718473A patent/DE2718473C3/en not_active Expired
-
1978
- 1978-04-20 CA CA301,578A patent/CA1094691A/en not_active Expired
- 1978-04-21 GB GB15861/78A patent/GB1560197A/en not_active Expired
- 1978-04-21 IT IT22617/78A patent/IT1095211B/en active
- 1978-04-24 JP JP4796778A patent/JPS53133341A/en active Granted
- 1978-04-24 SE SE7804620A patent/SE426107B/en unknown
- 1978-04-24 BR BR7802532A patent/BR7802532A/en unknown
- 1978-04-25 NL NL7804376A patent/NL7804376A/en not_active Application Discontinuation
- 1978-04-25 FR FR7812172A patent/FR2389285A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| SE7804620L (en) | 1978-10-27 |
| GB1560197A (en) | 1980-01-30 |
| JPS5759572B2 (en) | 1982-12-15 |
| IT7822617A0 (en) | 1978-04-21 |
| JPS53133341A (en) | 1978-11-21 |
| IT1095211B (en) | 1985-08-10 |
| DE2718473A1 (en) | 1978-11-02 |
| DE2718473B2 (en) | 1979-05-17 |
| NL7804376A (en) | 1978-10-30 |
| BR7802532A (en) | 1978-12-12 |
| FR2389285B1 (en) | 1981-08-14 |
| DE2718473C3 (en) | 1980-01-24 |
| FR2389285A1 (en) | 1978-11-24 |
| SE426107B (en) | 1982-12-06 |
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