GB2127594A

GB2127594A - Distribution of clock pulses

Info

Publication number: GB2127594A
Application number: GB08323715A
Authority: GB
Inventors: Graham Philip Abraham; Malcolm Eadie Brigham
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1982-09-18
Filing date: 1983-09-05
Publication date: 1984-04-11
Also published as: GB8323715D0; GB2127594B

Abstract

In a digital computer system, the clock pulses arriving at each individual module 10 are sampled at 19 and compared at 20 with the clock pulses obtained directly from the clock circuit 14. The transit times of the clock pulses are adjusted (by programmable delay 18) until the two sets of pulses coincide, indicating that the delay between the two sets of pulses is equal to an integral number (usually one) of clock periods. Thus, the period of the clock is used as a reference value for setting up the transit times of the pulses. The clock frequency may be first adjusted from its normal operational value so as to set the period at the desired value. <IMAGE>

Description

SPECIFICATION Distribution of clock pulses in a digital computer This invention relates to the distribution of clock pulses in a digital computer and more specifically is concerned with the adjustment of the transit times of these pulses.

A digital computer generally includes a clock circuit for producing a regular stream of clock pulses determining the rate of operation of the system. These pulses must be distributed via suitable wires, tracks and components to the various modules which make up the system.

However, it is very difficult to ensure that these wires, tracks and components are all of the same delay, and hence the transit times of the pulses between the central clock circuit and the respective modules may vary considerably. This can cause severe problems, especially in highspeed systems.

One solution to this problem has been suggested in United States Patent No.

4,063,308. In that patent, a programmable delay chip is introduced between the source of clock pulses and the logic chips to which the clock pulses are supplied. The clock pulses are also fed to a reference delay generator which delays them by a presettable amount. The distributed clock pulses are compared with the output of the reference delay generator, and the programmable delay chip is adjusted until the two sets of pulses coincide. In this way, the transit times of the clock pulses can be adjusted to the desired value.

One object of the present invention is to provide a simplified method of adjusting the transit times of the clock pulses, which does not require a reference delay generator.

Summary of the invention According to the invention, in a digital computer comprising: - a clock circuit producing a sequence of clock pulses, - a plurality of functional modules, ~means for distributing the clock pulses to the functional modules, and - a plurality of adjustable delay circuits for adjusting the transit times of the clock pulses between the clock circuit and the respective modules, the delay circuits are adjusted to make the transit times substantially equal, by a method comprising the steps:: ~sampling the clock pulses arriving at each functional module, ~comparing the sampled pulses with the clock pulses obtained directly from the clock circuit, and ~adjusting the delay circuits until the sampled clock pulses are aligned with the clock pulses obtained directly from the clock circuit.

Preferably, the comparison is performed by comparing the arrival times of the edges of the sampled and direct clock pulses, and the adjustment is performed so as to bring these edges into coincidence. For this purpose, either the rising edges or the falling edges of the pulses may be used. It will be seen that if the rising edges (or falling edges) of both sets of pulses are brought into alignment, the delay between the two sets of pulses must be equal to an integral number of periods of the clock frequency.

Alternatively, if the rising edges of one set of pulses are brought into alignment with the falling edges of the other set, the delay must be equal to a half-integral number of periods (assuming that the clock pulses have a 50% duty cycle).

For example, in one embodiment of the invention, the rising edges of the pulses are used, and the adjustable delay circuits are adjusted by gradually increasing their delays until the first coincidence occurs between the edges of the pulses, indicating that the delay between the two sets of pulses is just one clock period.

It can be seen that the invention removes the need for a reference delay generator by using the period of the clock itself as a reference value for setting up the transit times of the clock pulses.

Preferably, the clock frequency is first adjusted from its normal operational value so as to make the clock period correspond to the desired value of the transit times of the clock pulses.

Brief description of the drawings One embodiment of the invention will now be described by way of example with reference to the accompanying drawings of which: Figure 1 is a schematic diagram of a digital computer, showing the way in which clock pulses are distributed, and Figure 2 is a timing diagram showing the clock pulses and illustrating the method of adjusting the transit times.

Detailed description Referring to Figure 1, the computer comprises a plurality of modules 10, each consisting of a printed circuit board 1 1 carrying a number of integrated circuit chips 12. The functions of the various chips 12 and the way in which they are interconnected form no part of the present invention and so will not be described here. The modules 10 are in turn interconnected by larger printed circuit boards, referred to as mother boards 13, each of which carries a plurality of modules 10.

The computer has a clock circuit 14 which produces a stream of clock pulses for controlling the timing of the system. The frequency of the clock for normal operation is 24 MHz (corresponding to a period of 42 nanoseconds).

The clock frequency is adjustable in 1 MHz steps, through a range of +50% of the normal frequency.

The clock pulses are distributed to the various mother boards 13 by means of a set of gates 1 5 which fan-out the pulses to the boards 13. On each mother board, another set of gates 16 provides the necessary fan-out for distributing the clock pulses to the individual modules 10. Finally, in each module, a set of gates 17 provides the necessary fan-out for distributing the clock pulses to the individual chips 12.

It can be seen that the clock pulses pass through several gates and travel along various printed circuit board tracks before reaching the modules. The transit times along these paths are difficult to control and as a result there may be considerable variation in the times of arrival of the pulses at the individual modules. To compensate for this variation, each module has a programmable delay 18 which can be adjusted to vary the time of arrival of the pulses. Each delay is separately adjustable in increments of 400 picoseconds up to a maximum delay of approximately 50 nanoseconds.

Each module 10 has a feedback point 19 connected to a spare one of the fan-out gates 17.

These feedback points can be used for sampling the distributed clock pulses arriving at any of the modules.

The system also includes a comparator circuit 20. One input of the comparator is connected directly to the clock circuit 14 so as to receive the undistributed clock pulses. These undistributed pulses act as a reference signal for the comparator. The other input of the comparator is connected to a test lead 21. The test lead is a length of co-axial cable which can be connected to any one of the feedback points 19 so as to sample the distributed clock pulses at that point.

The comparator 20 comprises a D-type bistable circuit 22. The sampled clock pulses from the test lead 21 are applied to the data input of the bistable 22, while the reference pulses from the clock circuit are applied to the trigger input.

The bistable 22 is triggered on the rising edge of the reference pulse. The comparator 20 also includes a second D-type bistable 23, similar to the first bistable, but with a 1.0 nanosecond delay 24 at its trigger input to delay the arrival of the reference pulses.

The two inputs of the comparator 20 can be selectively inverted by means of a pair of equivalence gates 25, 26. The purpose of this will be explained later, but for the moment it will be assumed that the control inputs of both these gates are set to "1", so that the gates simply pass the input signals to the bistables 22, 23 without modification.

The outputs of the bistables 22, 23 are fed to respective bistables 27, 28 which are used as a buffer for preserving the value of the comparator output.

Operation The manner in which the transit times are adjusted will now be described.

First, the frequency of the clock 14 is altered from its normal operating value, to a value such that the clock period is equal to the required delay between the sampled and reference pulses. The test lead is then connected to one of the feedback points 19.

Two clock pulses are now produced by the clock circuit and applied to the system. Figure 2, trace (a) shows the clock pulses as they appear at the reference input of the comparator 20, while trace (c) shows the distributed pulses sampled by the test lead 21 as they appear at the other input of the comparator. The sampled pulses are delayed with respect to the reference pulses by an amount equal to the transit time between the clock circuit 14 and the module 10, plus the delay introduced by the test lead 21. As shown, the rising edge of the second reference pulse (a) occurs during the first sampled pulse (c). Since the bistable 22 is triggered by the rising edge of the reference pulse, it will be left in the "set" condition by these signals.

The programmable delay 18 is then adjusted so as to increase the delay by one increment, and two clock pulses are again applied as described above. This procedure is repeated, with successively increasing delays, until eventually it is found that bistable 22 is left in the "unset" condition. This occurs when the rising edge of the first sampled pulse falls just after the rising edge of the second reference pulse, as illustrated in trace (d) of Figure 2.

Trace (b) in Figure 2 shows the delayed reference signal which appears at the trigger input of the second bistable 23 in the comparator.

It can be seen that the rising edge of the second pulse of this signal still occurs during the first pulse of the sampled signal (d) and hence the bistable 23 will still remain in the "set" condition.

This provides a check that the rising edge of the sampled pulse (d) falls within the 1.0 nanosecond wide window defined by the delay 24, as shown by the two dashed vertical lines in Figure 2. The delay between the two sets of pulses is therefore substantially equal to one clock period.

The delay set on the programmable delay line 1 8 is recorded for future reference.

The procedure described above is then repeated for each of the modules in turn, using the same setting for the clock frequency, and using the same test lead 21. It can be seen that, in this way, the transit times of the clock signals to all the modules are adjusted to substantially the same value.

The recorded values of the delays can then be used, each time the computer is switched on, to set the delays 18 to their correct values, without the necessity for repeating the comparison procedure. It only becomes necessary to repeat the comparison procedure if one or more modules or motherboards are replaced or modified.

The procedure described above is preferably controlled by a specially programmed microprocessor 30, which receives the outputs from the comparator 20 and which sends control signals to the delays 18 to control the delay values and to the clock 14 to control the clock frequency. However, details of the microprocessor form no part of the present invention and so will not be described herein.

It was mentioned above that the gates 25, 26 permit the inputs to the two bistables 22, 23 to be selectively inverted. This enables the comparisons to be made not only between the rising edges of the reference and sampled pulses as described above, but also between the falling edges, or between the rising edge of one and the falling edge of the other, if so required.

Claims

1. In a digital computer comprising: - a clock circuit producing a sequence of clock pulses, - a plurality of functional modules, ~means for distributing the clock pulses to the functional modules, and - a plurality of adjustable delay circuits for adjusting the transit times of the clock pulses between the clock circuit and the respective modules, a method of adjusting the delay circuits to make the transit times substantially equal, comprising the steps:: ~sampling the clock pulses arriving at each functional module, ~comparing the sampled pulses with the clock pulses obtained directly from the clock circuit, and ~adjusting the delay circuits until the sampled clock pulses are aligned with the clock pulses obtained directly from the clock circuit.

2. A method according to Claim 1 wherein the comparison is performed by comparing the arrival times of the edges of the sampled and direct clock pulses, and the adjustment is performed so as to bring these edges into coincidence.

3. A method according to Claim 1 or 2 wherein the clock frequency is first adjusted from its normal operational value so as to make the clock period correspond to the desired value of the transit times of the clock pulses.

4. A method substantially as hereinbefore described with reference to the accompanying drawings.

5. Digital computer apparatus comprising: - a clock circuit for producing a sequence of clock pulses, -a a plurality of functional modules, ~means for distributing the clock pulses to the functional modules, - a plurality of adjustable delay circuits for adjusting the transit times of the clock pulses between the clock circuit and the respective modules, ~means for sampling the clock pulses arriving at any of the functional modules, - a comparator arranged to compare the sampled pulses with the clock pulses obtained directly from the clock circuit, and ~control means arranged to adjust the adjustable delay circuits until the comparator indicates that the sampled clock pulses are aligned with the clock pulses obtained directly from the clock circuit.

6. Apparatus according to Claim 5 wherein the comparator comprises a bistable circuit having a data input which receives the sampled pulses and a trigger input which receives the clock pulses obtained directly from the clock circuit.

7. Apparatus according to Claim 5 wherein the phase comparator further includes a further bistable circuit having a data input which receives the sampled pulses and a trigger input which receives the output of a delay line the input of which receives the clock pulses obtained directly from the clock circuit.

8. Apparatus according to any one of Claims 5 to 7 wherein the phase comparator includes means for inverting either the sampled pulses or the clock pulses obtained directly from the clock circuit.

9. Apparatus according to any one of Claims 5 to 8 wherein said control means comprises a microprocessor.

10. Digital computer apparatus substantially as hereinbefore described with reference to the accompanying drawings.