JP2013149310A5 - - Google Patents

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Publication number
JP2013149310A5
JP2013149310A5 JP2012008277A JP2012008277A JP2013149310A5 JP 2013149310 A5 JP2013149310 A5 JP 2013149310A5 JP 2012008277 A JP2012008277 A JP 2012008277A JP 2012008277 A JP2012008277 A JP 2012008277A JP 2013149310 A5 JP2013149310 A5 JP 2013149310A5
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JP
Japan
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clock
signal
output
semiconductor device
stage
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JP2012008277A
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English (en)
Japanese (ja)
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JP5932347B2 (ja
JP2013149310A (ja
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Priority to JP2012008277A priority Critical patent/JP5932347B2/ja
Priority claimed from JP2012008277A external-priority patent/JP5932347B2/ja
Priority to US13/743,052 priority patent/US8937843B2/en
Publication of JP2013149310A publication Critical patent/JP2013149310A/ja
Publication of JP2013149310A5 publication Critical patent/JP2013149310A5/ja
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JP2012008277A 2012-01-18 2012-01-18 半導体装置 Active JP5932347B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012008277A JP5932347B2 (ja) 2012-01-18 2012-01-18 半導体装置
US13/743,052 US8937843B2 (en) 2012-01-18 2013-01-16 Semiconductor device having counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012008277A JP5932347B2 (ja) 2012-01-18 2012-01-18 半導体装置

Publications (3)

Publication Number Publication Date
JP2013149310A JP2013149310A (ja) 2013-08-01
JP2013149310A5 true JP2013149310A5 (enExample) 2015-01-22
JP5932347B2 JP5932347B2 (ja) 2016-06-08

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JP2012008277A Active JP5932347B2 (ja) 2012-01-18 2012-01-18 半導体装置

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US (1) US8937843B2 (enExample)
JP (1) JP5932347B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102103415B1 (ko) * 2013-10-07 2020-04-23 에스케이하이닉스 주식회사 반도체 장치, 메모리 장치 및 이를 포함하는 시스템
US9036434B1 (en) * 2013-10-31 2015-05-19 Nanya Technology Corporation Random access memory and method of adjusting read timing thereof
KR102190962B1 (ko) 2013-12-30 2020-12-14 삼성전자주식회사 코맨드 처리 회로 및 이를 포함하는 메모리 장치
US9570135B2 (en) * 2014-02-06 2017-02-14 Micron Technology, Inc. Apparatuses and methods to delay memory commands and clock signals
JP6268020B2 (ja) * 2014-03-26 2018-01-24 ラピスセミコンダクタ株式会社 クロック生成方法および半導体装置
KR102647421B1 (ko) * 2016-10-06 2024-03-14 에스케이하이닉스 주식회사 반도체장치
US10607671B2 (en) 2018-02-17 2020-03-31 Micron Technology, Inc. Timing circuit for command path in a memory device
KR102638792B1 (ko) * 2018-10-01 2024-02-21 에스케이하이닉스 주식회사 반도체장치
US11217298B2 (en) * 2020-03-12 2022-01-04 Micron Technology, Inc. Delay-locked loop clock sharing
CN115705876A (zh) * 2021-08-03 2023-02-17 西安紫光国芯半导体有限公司 一种延迟校准电路、存储器和时钟信号校准方法
US12387769B2 (en) * 2022-05-23 2025-08-12 Changxin Memory Technologies, Inc. Latency adjustment method, memory chip architecture, and semiconductor memory
CN117894351A (zh) * 2022-10-08 2024-04-16 长鑫存储技术有限公司 一种延时控制电路、方法和半导体存储器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62223900A (ja) * 1986-03-26 1987-10-01 Hitachi Ltd 可変遅延段数シフトレジスタ
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JPH0866049A (ja) * 1994-08-18 1996-03-08 Sanyo Electric Co Ltd 系統連系インバータの力率制御回路
JP2002157900A (ja) * 2000-09-08 2002-05-31 Mitsubishi Electric Corp 半導体集積回路装置
US20020093994A1 (en) * 2000-12-30 2002-07-18 Norm Hendrickson Reverse data de-skew method and system
JP4828203B2 (ja) * 2005-10-20 2011-11-30 エルピーダメモリ株式会社 同期型半導体記憶装置
KR100818800B1 (ko) * 2006-06-27 2008-04-01 삼성전자주식회사 Ｆｉｆｏ 장치를 구비하는 데이터 처리장치와 데이터처리방법
JP2009020932A (ja) * 2007-07-10 2009-01-29 Elpida Memory Inc レイテンシカウンタ及びこれを備える半導体記憶装置、並びに、データ処理システム
US7715272B2 (en) 2008-05-22 2010-05-11 Elpida Memory, Inc. Semiconductor device having latency counter
US7864623B2 (en) 2008-05-22 2011-01-04 Elpida Memory, Inc. Semiconductor device having latency counter

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