JP2017507323A5 - - Google Patents

Download PDF

Info

Publication number
JP2017507323A5
JP2017507323A5 JP2016544161A JP2016544161A JP2017507323A5 JP 2017507323 A5 JP2017507323 A5 JP 2017507323A5 JP 2016544161 A JP2016544161 A JP 2016544161A JP 2016544161 A JP2016544161 A JP 2016544161A JP 2017507323 A5 JP2017507323 A5 JP 2017507323A5
Authority
JP
Japan
Prior art keywords
scan
output
circuit
clock
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016544161A
Other languages
English (en)
Japanese (ja)
Other versions
JP6521983B2 (ja
JP2017507323A (ja
Filing date
Publication date
Priority claimed from US14/145,293 external-priority patent/US9261560B2/en
Application filed filed Critical
Publication of JP2017507323A publication Critical patent/JP2017507323A/ja
Publication of JP2017507323A5 publication Critical patent/JP2017507323A5/ja
Application granted granted Critical
Publication of JP6521983B2 publication Critical patent/JP6521983B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2016544161A 2013-12-31 2014-12-31 最適周波数での一層遅いスキャン出力ハンドリング Active JP6521983B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/145,293 US9261560B2 (en) 2013-12-31 2013-12-31 Handling slower scan outputs at optimal frequency
US14/145,293 2013-12-31
PCT/US2014/073090 WO2015103440A1 (en) 2013-12-31 2014-12-31 Handling slower scan outputs at optimal frequency

Publications (3)

Publication Number Publication Date
JP2017507323A JP2017507323A (ja) 2017-03-16
JP2017507323A5 true JP2017507323A5 (enExample) 2018-02-15
JP6521983B2 JP6521983B2 (ja) 2019-05-29

Family

ID=53481402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016544161A Active JP6521983B2 (ja) 2013-12-31 2014-12-31 最適周波数での一層遅いスキャン出力ハンドリング

Country Status (5)

Country Link
US (1) US9261560B2 (enExample)
EP (1) EP3090268B1 (enExample)
JP (1) JP6521983B2 (enExample)
CN (1) CN105874343B (enExample)
WO (1) WO2015103440A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9448284B2 (en) * 2014-05-08 2016-09-20 Texas Instruments Incorporated Method and apparatus for test time reduction using fractional data packing
EP3153873A1 (en) * 2015-10-07 2017-04-12 Lantiq Beteiligungs-GmbH & Co. KG On-chip test pattern generation
US10060979B2 (en) 2016-08-02 2018-08-28 Texas Instruments Incorporated Generating multiple pseudo static control signals using on-chip JTAG state machine
US11073557B2 (en) * 2019-05-08 2021-07-27 Texas Instruments Incorporated Phase controlled codec block scan of a partitioned circuit device
JP1656709S (enExample) * 2019-05-31 2020-04-06
JP2021038982A (ja) * 2019-09-02 2021-03-11 株式会社東芝 半導体装置
US12175176B2 (en) * 2021-03-17 2024-12-24 Synopsys, Inc. Fast synthesis of logical circuit design with predictive timing
TWI800925B (zh) * 2021-09-17 2023-05-01 瑞昱半導體股份有限公司 測試系統以及測試方法
EP4232833B1 (en) * 2022-01-05 2024-10-09 Google LLC High-throughput scan architecture
US12203985B1 (en) 2023-07-17 2025-01-21 Stmicroelectronics International N.V. Test-time optimization with few slow scan pads

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59211147A (ja) * 1983-05-16 1984-11-29 Fujitsu Ltd スキヤンアドレス生成方式
US5663966A (en) * 1996-07-24 1997-09-02 International Business Machines Corporation System and method for minimizing simultaneous switching during scan-based testing
JP3196013B2 (ja) * 1996-12-12 2001-08-06 株式会社日立製作所 論理集積回路
US6694467B2 (en) * 1999-06-24 2004-02-17 Texas Instruments Incorporated Low power testing of very large circuits
JP3845016B2 (ja) * 1999-11-23 2006-11-15 メンター・グラフィクス・コーポレーション テスト中回路技術分野へのテストパターンの連続的な適用およびデコンプレッション
US6545549B2 (en) * 2000-03-02 2003-04-08 Texas Instruments Incorporated Remotely controllable phase locked loop clock circuit
US6766487B2 (en) * 2000-03-09 2004-07-20 Texas Instruments Incorporated Divided scan path with decode logic receiving select control signals
EP1146343B1 (en) * 2000-03-09 2005-02-23 Texas Instruments Incorporated Adapting Scan-BIST architectures for low power operation
US8091002B2 (en) * 2001-02-15 2012-01-03 Syntest Technologies, Inc. Multiple-capture DFT system to reduce peak capture power during self-test or scan test
JP2004093351A (ja) * 2002-08-30 2004-03-25 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
US7231570B2 (en) * 2004-05-26 2007-06-12 Syntest Technologies, Inc. Method and apparatus for multi-level scan compression
JP2006003317A (ja) * 2004-06-21 2006-01-05 Renesas Technology Corp スキャンテスト回路
EP1994419B1 (en) * 2006-02-17 2013-11-06 Mentor Graphics Corporation Multi-stage test response compactors
US7404126B2 (en) * 2006-03-29 2008-07-22 Texas Instruments Incorporated Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs
US7793179B2 (en) * 2006-06-27 2010-09-07 Silicon Image, Inc. Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers
US7372305B1 (en) * 2006-10-31 2008-05-13 International Business Machines Corporation Scannable dynamic logic latch circuit
US7823034B2 (en) * 2007-04-13 2010-10-26 Synopsys, Inc. Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
JP2009222644A (ja) * 2008-03-18 2009-10-01 Toshiba Corp 半導体集積回路、及び設計自動化システム
US8726112B2 (en) * 2008-07-18 2014-05-13 Mentor Graphics Corporation Scan test application through high-speed serial input/outputs
US8856601B2 (en) 2009-08-25 2014-10-07 Texas Instruments Incorporated Scan compression architecture with bypassable scan chains for low test mode power
US8205125B2 (en) * 2009-10-23 2012-06-19 Texas Instruments Incorporated Enhanced control in scan tests of integrated circuits with partitioned scan chains
US8458543B2 (en) 2010-01-07 2013-06-04 Freescale Semiconductor, Inc. Scan based test architecture and method
US8464117B2 (en) * 2010-05-25 2013-06-11 Freescale Semiconductor, Inc. System for testing integrated circuit with asynchronous clock domains
US8887018B2 (en) 2010-06-11 2014-11-11 Texas Instruments Incorporated Masking circuit removing unknown bit from cell in scan chain
US8887019B2 (en) * 2010-11-16 2014-11-11 Cadence Design Systems, Inc. Method and system for providing efficient on-product clock generation for domains compatible with compression
US9746519B2 (en) * 2011-03-25 2017-08-29 Nxp B.V. Circuit for securing scan chain data
US8671320B2 (en) 2011-06-21 2014-03-11 Lsi Corporation Integrated circuit comprising scan test circuitry with controllable number of capture pulses
JP6221433B2 (ja) * 2013-07-09 2017-11-01 株式会社ソシオネクスト 半導体集積回路

Similar Documents

Publication Publication Date Title
JP2017507323A5 (enExample)
CN103378826B (zh) 高精度单沿捕获以及延迟测量电路
JP2013149310A5 (enExample)
JP2011071995A5 (ja) カウンタ回路
CN111600699B (zh) 用于实现散列算法的电路和方法
US9377997B2 (en) Random number generator
CN108226763B (zh) 用于扫描链重新排序的方法、设备和计算机程序产品
US10445068B2 (en) Random number generator
JP2015534673A5 (enExample)
US20100201419A1 (en) Apparatus and method for generating random number
US12474404B2 (en) Test circuit, test method, and computing system comprising test circuit for testing sequential circuit in pipeline stage
KR102711536B1 (ko) 타이밍 데이터 수집 장치
JP5670849B2 (ja) 擬似乱数生成装置、および、擬似乱数生成方法
DE602007003319D1 (de) Frequenzteilerschaltungen
JP6423270B2 (ja) 乱数生成装置及び乱数生成方法
US20150061740A1 (en) Scannable flop with a single storage element
CN104579295A (zh) 时钟动态切换电路及方法
Tupparwar et al. A hybrid true random number generator using ring oscillator and digital clock manager
US9347991B1 (en) Scan throughput enhancement in scan testing of a device-under-test
JP2011248579A5 (enExample)
JP2015099146A5 (enExample)
JP6379032B2 (ja) 乱数生成装置及び乱数生成方法
JP6575970B2 (ja) 試験時間削減のための方法及び装置
Cartagena et al. A fully-synthesized TRNG with lightweight cellular-automata based post-processing stage in 130nm CMOS
US9966964B1 (en) Multi-phase divider