TWI800925B - 測試系統以及測試方法 - Google Patents

測試系統以及測試方法 Download PDF

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Publication number
TWI800925B
TWI800925B TW110134720A TW110134720A TWI800925B TW I800925 B TWI800925 B TW I800925B TW 110134720 A TW110134720 A TW 110134720A TW 110134720 A TW110134720 A TW 110134720A TW I800925 B TWI800925 B TW I800925B
Authority
TW
Taiwan
Prior art keywords
test
syatem
test method
test syatem
Prior art date
Application number
TW110134720A
Other languages
English (en)
Other versions
TW202314726A (zh
Inventor
羅宇誠
Original Assignee
瑞昱半導體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞昱半導體股份有限公司 filed Critical 瑞昱半導體股份有限公司
Priority to TW110134720A priority Critical patent/TWI800925B/zh
Priority to US17/946,055 priority patent/US20230092349A1/en
Publication of TW202314726A publication Critical patent/TW202314726A/zh
Application granted granted Critical
Publication of TWI800925B publication Critical patent/TWI800925B/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
TW110134720A 2021-09-17 2021-09-17 測試系統以及測試方法 TWI800925B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW110134720A TWI800925B (zh) 2021-09-17 2021-09-17 測試系統以及測試方法
US17/946,055 US20230092349A1 (en) 2021-09-17 2022-09-16 System and method which can reduce circuit area while performing test function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110134720A TWI800925B (zh) 2021-09-17 2021-09-17 測試系統以及測試方法

Publications (2)

Publication Number Publication Date
TW202314726A TW202314726A (zh) 2023-04-01
TWI800925B true TWI800925B (zh) 2023-05-01

Family

ID=85572702

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110134720A TWI800925B (zh) 2021-09-17 2021-09-17 測試系統以及測試方法

Country Status (2)

Country Link
US (1) US20230092349A1 (zh)
TW (1) TWI800925B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230005562A1 (en) * 2021-07-05 2023-01-05 Synopsys, Inc. Scan chain compression for testing memory of a system on a chip

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW594774B (en) * 2001-05-21 2004-06-21 Infineon Technologies Ag The method for testing a data memory
US7712001B2 (en) * 2005-02-23 2010-05-04 Nec Electronics Corporation Semiconductor integrated circuit and method of testing semiconductor integrated circuit
US20110145774A1 (en) * 2003-02-13 2011-06-16 Mentor Graphics Corporation Testing embedded memories in an integrated circuit
US20150269991A1 (en) * 2014-03-21 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Memory unit and method of testing the same
US20190120902A1 (en) * 2017-08-09 2019-04-25 Micron Technology, Inc. Scan chain operations
US20210074353A1 (en) * 2018-04-18 2021-03-11 Arm Limited Latch Circuitry for Memory Applications
TWI739716B (zh) * 2021-03-03 2021-09-11 瑞昱半導體股份有限公司 測試電路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9261560B2 (en) * 2013-12-31 2016-02-16 Texas Instruments Incorporated Handling slower scan outputs at optimal frequency
US9666302B1 (en) * 2015-12-28 2017-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for memory scan design-for-test
US9941866B2 (en) * 2016-07-12 2018-04-10 Qualcomm Incorporated Apparatus for design for testability of multiport register arrays
CN107783030B (zh) * 2016-08-29 2021-04-23 恩智浦美国有限公司 具有低功率扫描系统的集成电路
JP6702560B2 (ja) * 2017-02-21 2020-06-03 株式会社東芝 半導体集積回路
TWI689738B (zh) * 2019-02-21 2020-04-01 瑞昱半導體股份有限公司 測試系統
US11073557B2 (en) * 2019-05-08 2021-07-27 Texas Instruments Incorporated Phase controlled codec block scan of a partitioned circuit device
US10852353B1 (en) * 2019-07-02 2020-12-01 Texas Instruments Incorporated Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface
US11714125B2 (en) * 2020-05-12 2023-08-01 Mediatek Inc. Multi-bit flip-flop with power saving feature
US11726140B2 (en) * 2021-02-01 2023-08-15 Stmicroelectronics International N.V. Scan circuit and method
US20230005562A1 (en) * 2021-07-05 2023-01-05 Synopsys, Inc. Scan chain compression for testing memory of a system on a chip

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW594774B (en) * 2001-05-21 2004-06-21 Infineon Technologies Ag The method for testing a data memory
US20110145774A1 (en) * 2003-02-13 2011-06-16 Mentor Graphics Corporation Testing embedded memories in an integrated circuit
US7712001B2 (en) * 2005-02-23 2010-05-04 Nec Electronics Corporation Semiconductor integrated circuit and method of testing semiconductor integrated circuit
US20150269991A1 (en) * 2014-03-21 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Memory unit and method of testing the same
US20190120902A1 (en) * 2017-08-09 2019-04-25 Micron Technology, Inc. Scan chain operations
US20210074353A1 (en) * 2018-04-18 2021-03-11 Arm Limited Latch Circuitry for Memory Applications
TWI739716B (zh) * 2021-03-03 2021-09-11 瑞昱半導體股份有限公司 測試電路

Also Published As

Publication number Publication date
TW202314726A (zh) 2023-04-01
US20230092349A1 (en) 2023-03-23

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