JP2014520436A5 - - Google Patents

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Publication number
JP2014520436A5
JP2014520436A5 JP2014513786A JP2014513786A JP2014520436A5 JP 2014520436 A5 JP2014520436 A5 JP 2014520436A5 JP 2014513786 A JP2014513786 A JP 2014513786A JP 2014513786 A JP2014513786 A JP 2014513786A JP 2014520436 A5 JP2014520436 A5 JP 2014520436A5
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JP
Japan
Prior art keywords
coupled
switch
driven
weighted
clock signal
Prior art date
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Application number
JP2014513786A
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English (en)
Japanese (ja)
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JP6141833B2 (ja
JP2014520436A (ja
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Priority claimed from US13/153,190 external-priority patent/US8451042B2/en
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Publication of JP2014520436A publication Critical patent/JP2014520436A/ja
Publication of JP2014520436A5 publication Critical patent/JP2014520436A5/ja
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Publication of JP6141833B2 publication Critical patent/JP6141833B2/ja
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JP2014513786A 2011-06-03 2012-06-04 線形性が改善されたデジタル位相補間器のための装置及びシステム Active JP6141833B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/153,190 2011-06-03
US13/153,190 US8451042B2 (en) 2011-06-03 2011-06-03 Apparatus and system of implementation of digital phase interpolator with improved linearity
PCT/US2012/040718 WO2012167239A2 (en) 2011-06-03 2012-06-04 Apparatus and systems digital phase interpolator with improved linearity

Publications (3)

Publication Number Publication Date
JP2014520436A JP2014520436A (ja) 2014-08-21
JP2014520436A5 true JP2014520436A5 (enExample) 2015-07-16
JP6141833B2 JP6141833B2 (ja) 2017-06-07

Family

ID=47260431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014513786A Active JP6141833B2 (ja) 2011-06-03 2012-06-04 線形性が改善されたデジタル位相補間器のための装置及びシステム

Country Status (4)

Country Link
US (1) US8451042B2 (enExample)
JP (1) JP6141833B2 (enExample)
CN (1) CN103718460B (enExample)
WO (1) WO2012167239A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101326117B1 (ko) * 2013-06-25 2013-11-06 홍익대학교 산학협력단 위상 반전 록킹 알고리즘을 이용한 디지털 지연 고정 루프 회로 및 제어방법
US9407245B2 (en) * 2014-06-30 2016-08-02 Intel IP Corporation System for digitally controlled edge interpolator linearization
CN106936437A (zh) * 2015-12-31 2017-07-07 京微雅格（北京）科技有限公司 数模转换器、包括其的模数转换器及版图实现方法
KR102671076B1 (ko) * 2017-02-09 2024-05-30 에스케이하이닉스 주식회사 내부클럭생성회로
JP6902952B2 (ja) * 2017-07-20 2021-07-14 ローム株式会社 位相補間器およびタイミング発生器、半導体集積回路
US10483956B2 (en) 2017-07-20 2019-11-19 Rohm Co., Ltd. Phase interpolator, timing generator, and semiconductor integrated circuit
US11387841B2 (en) 2017-12-15 2022-07-12 Intel Corporation Apparatus and method for interpolating between a first signal and a second signal
CN108092649B (zh) * 2018-01-03 2021-05-04 龙迅半导体（合肥）股份有限公司 一种相位插值器和相位插值器的控制方法
US11088682B2 (en) 2018-12-14 2021-08-10 Intel Corporation High speed digital phase interpolator with duty cycle correction circuitry
US12176903B1 (en) * 2023-07-12 2024-12-24 Himax Technologies Limited Duty cycle correction device for use in cascaded circuits and related large touch and display driver integration system

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512860A (en) * 1994-12-02 1996-04-30 Pmc-Sierra, Inc. Clock recovery phase locked loop control using clock difference detection and forced low frequency startup
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US5945862A (en) 1997-07-31 1999-08-31 Rambus Incorporated Circuitry for the delay adjustment of a clock signal
CA2233831A1 (en) 1998-03-31 1999-09-30 Tom Riley Digital-sigma fractional-n synthesizer
JP3789247B2 (ja) * 1999-02-26 2006-06-21 Ｎｅｃエレクトロニクス株式会社 クロック周期検知回路
US6114914A (en) 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals
TW483255B (en) * 1999-11-26 2002-04-11 Fujitsu Ltd Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
JP3495311B2 (ja) * 2000-03-24 2004-02-09 Ｎｅｃエレクトロニクス株式会社 クロック制御回路
JP3498069B2 (ja) * 2000-04-27 2004-02-16 Ｎｅｃエレクトロニクス株式会社 クロック制御回路および方法
JP3450293B2 (ja) * 2000-11-29 2003-09-22 Ｎｅｃエレクトロニクス株式会社 クロック制御回路及びクロック制御方法
JP3636657B2 (ja) * 2000-12-21 2005-04-06 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路とそのクロック制御方法
KR100715845B1 (ko) 2001-02-17 2007-05-10 삼성전자주식회사 위상혼합기 및 이를 이용한 다중위상 발생기
US6952123B2 (en) * 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
US6911853B2 (en) * 2002-03-22 2005-06-28 Rambus Inc. Locked loop with dual rail regulation
US7295077B2 (en) 2003-05-02 2007-11-13 Silicon Laboratories Inc. Multi-frequency clock synthesizer
US20050093594A1 (en) 2003-10-30 2005-05-05 Infineon Technologies North America Corp. Delay locked loop phase blender circuit
US7750695B2 (en) * 2004-12-13 2010-07-06 Mosaid Technologies Incorporated Phase-locked loop circuitry using charge pumps with current mirror circuitry
US7596670B2 (en) 2005-11-30 2009-09-29 International Business Machines Corporation Restricting access to improve data availability
JP4684919B2 (ja) * 2006-03-03 2011-05-18 ルネサスエレクトロニクス株式会社 スペクトラム拡散クロック制御装置及びスペクトラム拡散クロック発生装置
US7417510B2 (en) 2006-09-28 2008-08-26 Silicon Laboratories Inc. Direct digital interpolative synthesis
US7764134B2 (en) 2007-06-14 2010-07-27 Silicon Laboratories Inc. Fractional divider
JP5451012B2 (ja) * 2008-09-04 2014-03-26 ピーエスフォー ルクスコ エスエイアールエル Ｄｌｌ回路及びその制御方法
US8258839B2 (en) * 2010-10-15 2012-09-04 Texas Instruments Incorporated 1 to 2N-1 fractional divider circuit with fine fractional resolution

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