Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/131—Digitally controlled
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
  • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
  • H03K2005/00019—Variable delay
  • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
  • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal

Definitions

• This application is directed, in general, to a digital phase interpolator and, more specifically, to a digital phase interpolator with an improved linear response.
• Phase locked loops have been used for frequency synthesis in many conventional circuits, and these PLLs generally included internal and/or external dividers. These PLLs (and the corresponding dividers) have also been used to generate fractional frequencies, but, usually, at a price (namely, spurs and jitter). Therefore, there is a need for an improved fractional divider that can be used with or within a PLL or reference clock generator. There is also a need for an improved digital phase interpolator with improved linearity to be used in design of such fractional dividers and other circuits where intermediate finer phase steps need to be derived from the available clock phases.
• Garlepp et al "A Portable Digital DLL for High-Speed CMOS Interface Circuits", IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, May 1999, pp. 632-644; Garlepp et al, "A Portable Digital DLL Architecture for CMOS Interface Circuits", IEEE 1998 Symposium on VLSI Circuits Digest of Technical papers,, pages 214-215; Saeki, et al., "A 1.3-Cycle Lock Time, Non-PLL/DLL Clock Multiplier Based on Direct Clock Cycle Interpolation for 'Clock on Demand'"; IEEE Journal of Solid-State Circuits, Vol. 35, November 200, pp.
• a first aspect provides an apparatus comprising: a control switch driven by a bit value; a weighted switch driven by a clock signal; an intermediate node coupled between the control switch and the weighted switch; and a pre-charge transistor coupled to the intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal.
• the first aspect further provides wherein the control switch and the weighted switch are coupled to a capacitor.
• a circuit pre-charge transistor is coupled to the capacitor that can pre-charge the capacitor. The pre-charge transistor is transitioned on when the control switch and the weighted switch are driven off.
• the first aspect still further provides: a second control switch driven by an inverted bit value; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; and a second pre-charge transistor coupled to the intermediate node, wherein the pre-charge transistor is driven by an inverse of the second clock signal, wherein the first weighted switch has substantially a same capacitance as the second weighted switch.
• the capacitor is coupled to an inverter to generate a blended phase output of the first clock signal and the second clock signal.
• the bit value is part of a control word.
• a second aspect provides an apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first pre-charge transistor coupled to the first intermediate node, wherein the pre-charge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit of the logical unit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second pre-charge transistor coupled to the second intermediate node, wherein the second pre-charge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first pre-charge transistor and the second pre-charge transistor.
• the second aspect further provides a circuit pre-charge transistor coupled to the capacitor that can pre-charge the capacitor.
• the pre-charge transistor is transitioned upon the control switch and the weighted switch both being driven off.
• the capacitor is coupled to an inverter to generate a blended phase output of the first clock signal and the second clock signal.
• the first bit value is part of a control word.
• a third aspect provides a system, comprising: a delay locked loop (DLL) having a plurality of taps; a phase blender that is coupled to receive signals from consecutive taps of the DLL, the phase blender, including: a control switch driven by a bit value; a weighted switch driven by a clock signal; an intermediate node coupled between the control switch and the weighted switch; and a pre-charge transistor coupled to the intermediate node, wherein the pre- charge transistor is driven by an inverse of the clock signal, a state machine that is coupled to the phase blender so as to provide control word to the phase blender; a toggle circuit that is coupled to the phase blender and the state machine; a duty cycle correction circuit that is coupled to the toggle circuit; and a sigma delta modulator that is coupled to the toggle circuit and state machine.
• DLL delay locked loop
• the third aspect further provides wherein the control switch and the weighted switch are coupled to a capacitor.
• a circuit pre-charge transistor coupled to the capacitor that can pre-charge the capacitor. The pre-charge transistor is transitioned on when the control switch and the weighted switch are driven off.
• the third aspect still further provides: a second control switch driven by a second bit value; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; and a second pre- charge transistor coupled to the intermediate node, wherein the pre-charge transistor is driven by an inverse of the second clock signal, wherein the first weighted switch has substantially a same capacitance as the second weighted switch.
• the capacitor is coupled to an inverter to generate a blended phase output of the first clock signal and the second clock signal.
• the bit value is part of a control word.
• FIG. 1 illustrates an embodiment of a phase blender circuit employing pre-charge transistors coupled to their respective intermediate nodes
• FIG. 2 is an illustration of a timing diagram of a phase blending of FIG. 1;
• FIG. 3 is an embodiment of a digital phase interpolator that uses the phase blender circuit of FIG. 1;
• FIG. 4 is a graph of an interpolation error with and without the phase blender circuit of FIG. 1;
• FIG. 5 A is a graph of a prior art jitter of an interpolation circuit.
• FIG. 5B is a graph of jitter of an interpolation circuit that employs the phase blender circuit of FIG. 1.
• FIG. 1 illustrates a phase blender in the form of an example digital phase interpolator ("interpolator") 100.
• interpolator 100 an important parameter for the interpolator 100 is its linearity, i.e., how close to an ideal desired phase a blended output clock signal, such as an INT CLK, signal, is during an operation of the interpolator 100.
• the interpolator 100 employs a plurality of nMOS transistor switches (“control switches”) 111, 113, 115, 117, and control switches 121, 123, 125, 127, which are controlled by a control word: "SEL” and "SELZ” (i.e. an inverted SEL), respectively.
• a plurality of binary weighted clock nMOS transistor switches (“weighted switches”) 141, 143, 145, 147 and weighted switches 151, 153, 155 and 157 are controlled by clock inputs: CK0 and CK1, respectively, wherein the weighted switches 141-157 are coupled in series with the control switches 111-127.
• a plurality of nMOS intermediate node pre-charge transistors (“intermediate node pre-charge transistor”) 131-134 and a plurality of intermediate node pre-charge transistors 135- 138 are each, individually, coupled to each own's respective intermediate node 112-118 and intermediate node 122-128.
• the intermediate nodes 112-118 are coupled between its corresponding control switch 111-127 and its weighted switch 141-157, to pre-charge the intermediate nodes 112-118 and intermediate nodes 122-128.
• this pre- charge is one threshold voltage below a voltage supply VDD 159, as shall be explained in more detail below.
• a capacitor CO 158 is also provided at an output intermediate node 160,
• the capacitor CO 158 is pre-charged in a low cycle of the clock inputs CK0 and CK1 by a pMOS pre-charge transistor ("circuit pre-charge transistor") 163 that is coupled to the voltage supply VDD 159.
• circuit pre-charge transistor pMOS pre-charge transistor
• the gate of the circuit pre-charge transistor 163 is controlled by an OR of the two clock phases, CK0 and CK1. Once both these clocks CK0 and CK1 go low, the circuit pre-charge transistor 163 is closed and pulls up INTCKB high, before the next rising edges of CLKO and CK1 arrive. In other words, once both CKO and CK1 are low, Vdd voltage of the voltage supply VDD 159 of the circuit pre-charge transistor 163 is applied across CO 158.
• the OR is embodied as an output of a NOR gate 161 coupled to an input of an inverter 162.
• the interpolator 100 takes as inputs: two clocks signals, such as CKO and CK1, and a control word, such as "SEL" (and its logical inverse "SELZ"), and then produces a blended phase output clock signal INT CLK, wherein the phase of INT CLK is a linear function of the control words.
• the interpolator 100 may be used in various aspects where intermediate phases of a clock signal are needed.
• An example where a phase interpolator may be used is a fractional divider circuit described in to Lucas, U.S. Pat. Application Pub. No.: 2012/0092051, entitled “A 1 to 2 n -l fractional divider circuit with fine fractional resolution,” which is hereby incorporated herein by reference in its entirety.
• parasitic capacitances can be substantially non- interferingly discharged to ground if the control signal applied to a word switch is high, as there would be a complete path from an output capacitor to ground when the corresponding clock also goes high. In other words, if the clocked switch for a given weighted branch is on and the word switch is on, then there is a short in the line, and the parasitic capacitances at the internal node are discharged.
• a conventional phase blender circuit can exhibits a memory effect which introduces a dependence of the phase interpolator output phase, not only on the current control word but also on the previous control word.
• this introduces additional jitter, i.e. non-ideal placement of clock edges in time.
• these intermediate nodes 112-118 and 122-128 are pre-charged to one threshold voltage of the pre-charge transistors 131-138 below the voltage supply 159.
• the gates of these pre- charge transistors 131-138 are controlled by the inverted clock inputs CKOZ and CK1Z.
• CK0 1 and CKl l which are employed to control gates of the weighted switches 141-157, are also delayed relative to CK0 2 and CK1 2.
• CK0 2 and CK1 2 used to control the gate of the circuit pre-charge transistor 163. This is done to avoid any contention between the pre-charge path of the capacitor 159 and pull-down paths (i.e. a pull down path is when both the control switch 111-127 and its weighted switch 141-157 is on).
• a pMOS pre-charge transistor is on and conducting when a pull-down path is on
• a simultaneous pull-up path provided by a pMOS capacitor pre-charge transistor when conducting, would fight a discharge of a prior art intermediate node.
• the pull-up path may be a pMOS transistor whose gate is always connected to ground. Consequently, the pull-up path is always on.
• the discharge time of an intermediate node is not entirely controlled by the pull-down path, and therefore would not be entirely controlled by the digital control word. This is undesirable as it would make the final output phase of the prior art interpolator not directly proportional to the control word input, and non-linear.
• this undesirability is avoided by activating the circuit pre-charge transistor 163 only after the input clocks CK0 1 and CKl l both transition to a low state, at which time the pull-down path is already off.
• control words SEL and SELZ are set up and ready prior to the rising edge of the clock inputs, and are applied to control switches 111-117 and 121-127, respectively. Once the rising edges of CKO and CKl arrive at weighted switches 141-147, the control word SEL controls the relative contributions of the early (CKO) and late (CKl) clock inputs to the timing of the discharge of the capacitor CO 159.
• control words SEL and SELZ are set up and ready prior to the rising edge of the clock inputs, and are applied to control switches 111-117 and 121-127, respectively. Once the rising edges of CKO and CKl arrive at weighted switches 141-147, the control word SEL controls the relative contributions of the early (CKO) and late (CKl) clock inputs to the timing of the discharge of the capacitor CO 159. [0037] In the circuit 100, when the inverted input clocks CKOZ and CK1Z go low, the interpolation of the rising edge between the CKO and CK1 clock signals is complete. There is now an open circuit through weighted switches 141-147 and 151-157.
• the inverted clocks CKOZ and CK1Z go high, substantially simultaneously as the inverted input clocks CKOZ and CK1Z go low, allowing the precharging of the intermediate nodes 112-118 and intermediate nodes 122-128 all to the same voltage, regardless of any previously given control word or magnitude of parasitic capacitances at these intermediate nodes. Then, when the clock signals CKO and CK1 go high, CKOZ and CK1Z go low and turn off the pre-charge transistors 131-138, allowing the interpolation to take place based on a present control word input and the same internal charge state regardless of the control word.
• clocks signals are coupled to weighted switches 141-147 and
• control switches 111-117 and 121-127 are placed at the top. This is done so that there is no short circuit current due to its corresponding pre-charge transistor 131-138 and the bottom nMOS transistor weighted switches 141-157 being on at a same time.
• some of the control switches 111-117 are on and some are off depending on the control word, such as SEL, and control switches 121-127 are on and off depending upon an inverted control word, such as SELZ.
• pre-charge transistors 131-138 are on during low clock phase, half the time. Hypothetically, if control switches were placed on the bottom of a discharge path, the ones that are on for that particular control word would provide a complete short-circuit path from supply to ground in series with pre-charge transistors whenever the pre-charge transistors are high and these pre-charge transistors are also on. However, in order to avoid this hypothetical short circuit path, weighted switches 141-157 are placed on the bottom of a conductive path, and pre-charge transistors 131-138 are controlled by an inverse of a clock signal that drives weighted switches 141-157.
• weighted switches 141-157 are sized in direct proportion to a binary control bit of its corresponding control switch 111-127, e.g. if the width of weighted switch 141 is one unit, weighted switch 143 is sized to have a width of 2 units, weighted switch 145 is sized to have a width of 4 units, and weighted switch 147 is sized to have a width of 8 units.
• Weighted switches 151-157 are sized the same way proportional to their control bit. This allows digital control of the strength of the overall pull-down path consisting of nMOS transistors that are the weighted switches 141-157.
• each of the weighted switches 141-157 has a capacitance in proportion to its individual size. This in turn allows for digital control of the discharge time of node 160, which in turn controls output timing.
• gate lengths of transistor weighted switches 141-157 are kept the same and their widths are adjusted in proportion to the corresponding binary positions they represent in the control word.
• a control switch such as control switch 111
• a weighted switch such as weighted switch 141
• An intermediate node such as intermediate node 112 is coupled between the control switch 111 and the weighted switch 141.
• a pre-charge transistor such as pre-charge transistor 131, is coupled to the intermediate node 112, wherein the pre-charge transistor 131 is driven by an inverse of the clock signal.
• the control switch 111 and the weighted switch 141 are coupled to the capacitor 158.
• the capacitor pre-charge transistor 163 is coupled to the capacitor 158 that can pre-charge the capacitor 158.
• the pre-charge transistor 131 is transitioned to an on state when the control switch 111 and the weighted switch 141 are driven to an off state.
• the circuit 100 further includes a second control switch, such as control switch 121 driven by an inverted bit value; a second weighted switch, such as weighted switch 151, driven by a second clock signal; a second intermediate node, such as intermediate node 122, coupled between the second control switch 121 and the second weighted switch 151; and a second pre-charge transistor, such as pre-charge transistor 135, coupled to the intermediate node 122, wherein the pre-charge transistor 135 is driven by an inverse of the second clock signal.
• the first weighted switch 141 has substantially a same capacitance as the second weighted switch 151.
• the capacitor 158 is coupled to the first control switch 111, the second control switch 121, the first weighted transistor 141 and the second weighted transistor 151.
• the capacitor 158 is coupled to the inverter 165 to generate a blended phase output of the first clock signal and the second clock signal.
• the bit value is part of a control word.
• a third control switch such as control switch 113
• a third weighted switch such as weighted switch 143 is driven by the clock signal.
• a third intermediate node such as node 114, is coupled between the third control switch 113 and the third weighted switch 143.
• a third pre-charge transistor such as pre- charge transistor 132
• a fourth control switch such as control switch 123, is driven by an inverse of the second bit.
• a fourth weighted switch, such as weighted switch 151, is driven by the second clock signal.
• a fourth intermediate node such as node 124, is coupled between the fourth control switch 123 and the fourth weighted switch 153.
• a fourth pre-charge transistor such as pre-charge transistor 136, is coupled to said fourth intermediate node 124, wherein said fourth pre-charge transistor 136 is driven by an inverse of the second clock signal.
• the capacitor 158 is coupled to said third control switch 113, said fourth control switch 123, said third pre-charge transistor 132 and said fourth pre-charge transistor 136.
• the first weighted switch 141 has substantially twice a capacitance of the third weighted switch 143.
• FIG. 2 illustrated is one embodiment a timing diagram 200.
• the intermediate nodes 112-118 and intermediate nodes 122-128 are all pre-charged to one threshold voltage below the voltage supply 159 when the CK0Z and CK1Z clocks goes low.
• the intermediate nodes 112-118 and intermediate nodes 122-128 are selectively discharged to ground, depending on SEL by the high cycle of the input clocks CKO and CKl . Precharging of the nodes 112-118 and 122-128 in this fashion has the effect that charge state of all the intermediate nodes is the same for each interpolation regardless of the control word. Therefore the memory and the history effect are erased or substantially erased.
• a CKO signal is applied to weighted switches 141-147 and a CKl signal is applied to switches 151 to 157.
• PCHGZ is signal that is applied to pMOS pre-charge transistor 163.
• PCHGZ is a low active signal, i.e. capacitor pre-charge transistor 163 being a pMOS device is activated and on when PCHGZ is low. This happens when both CKO and CKl go low.
• INTCLKB node is a voltage value that drops when both CLK1 and CLK2 are applied. This occurs because either weighted switches 141 to 147 are on, or weighted transistors 151-157 are on, according to the SEL (and SELZ) command. A negative transition at internal node 158 starts after a rising edge of CKO and continues through a rising edge CK1, as determined by SEL command. Similarly, INTCLKB starts going high after both CKO and CK1 falling edges.
• the INTCLKB node 158 is pre-charged to VDD through a circuit pre-charge transistor, such as the pre-charge transistor 163.
• the gate of the circuit pre-charge transistor 163 is controlled by PCHGZ.
• the circuit pre-charge transistor 163 pulls INTCLKB node 158 high, setting it up for rising edge interpolation.
• internal nodes 112-128 are also pre- charged high to VDD-Vt (threshold voltage of the nMOS pre-charge transistor 131-138).
• the divider 300 generally comprises a prescaler 302, a delay locked loop (DLL) 304, a multiplexers or muxes 306 and 320, state machine 308, latches 310-1 to 310-R, phase blender or interpolator 312, toggle circuit 314, duty cycle correction circuit or DCC, and sigma-delta modulator or SDM 316, and divider 322.
• DLL delay locked loop
• a divider receives the clock signal PCLK from a PLL and generates a divided clock signal CLKOUT based on a control word DIV that indicates the magnitude of division.
• the control word DIV can, for example, be 30 bits long having 10 bits for an integer setting, 8 bits for a coarse fractional setting, and 12 bits for a fine fractional setting.
• the prescaler 302 divides the clock signal PCLK for use by the DLL 204 (e.g., divided by two).
• the DLL 304 which has several taps (i.e., 16), can generate several phases CLKl to CLKR of the prescaled clock signal (from prescaler 302) at these taps.
• Each of these phases CLKl to CLKR of the prescaled clock signal are generally provided to the input terminals of mux 306 and state machine 308.
• Each phase CLKl to CLKR can also be provided to a respective latch 310-1 to 310-R (which may be configured to operate as D flip-flops or latches depending on the fractional part of the divided ratio).
• the state machine 308 (which can receive the integer setting and coarse fractional setting from the control word DIV) controls the mux 306 (through latches 310-1 top 310-R with the use of select signals SEL1 to SELR) so as to select consecutive phases MCLK1 and MCLK2 (which, for example, can correspond to phases CLK(i) and CLK(i+l) from phases CLKl to CLKR that are input into mux 306.
• the phase blender 312 generally generates finer intermediate phases by interpolating the consecutive phases CKOand CK1, and the output INT CLK of phase blender 312 can then be used as a clocking signal for toggle circuit 314 (which may be a D flip-flop) that is enabled by the state machine 208 (which can provide enable signal EN).
• This output signal FRAC DIV from the toggle circuit 314 can then be provided to the DCC 318, and divider 320.
• Mux 320 can then select between the outputs of divider 320 (which can, for example, be a divide-by-2 divider) and the DCC 318 (which can be based on control word DIV) so as to refine the output clock signal CLKOUT.
• the output signal FRAC DIV of toggle circuit 214 can be provided to SDM 316 (which can also receive the fine fractional setting from control word DIV and which may be a first order SDM) so that the SDM 316 can provide a control signal to the state machine 208 to dither the output clock signal CLKOUT between two blended phases derived from consecutive phases CKO and CKl to generate the fine divide ratios and generally maintain a low deterministic jitter.
• SDM 316 which can also receive the fine fractional setting from control word DIV and which may be a first order SDM
• FIG. 4 illustrated is one example of a reduced jitter when using the circuit 100 as a phase blender 312 when compared to prior technologies.
• jitter noise can be reduced by a factor of, for example, 5, for the extreme cases.
• FIG. 5A illustrated is a prior art description of jitter.
• This figure shows an eye diagram where multiple periods of the output clock are folded back on top of each other. For an ideal output, all the edges would lie on top of each other. In a practical case, there is a broadening of the folded back edge due to non-idealities in timing. This is an indication of the timing jitter associated with this signal. As such, having a lower broadening of the folded back edges is desirable, i.e. lower jitter.
• FIG. 5A shows the eye diagram and associated jitter with it for the fractional divider output using the previous implementation of the phase interpolator.
• an ideal DLL Delay Locked Loop
• FIG. 5B shows the corresponding eye diagram and resulting jitter when using the phase interpolator described in Fig. 1.
• the phase interpolator described in this application results in a significant reduction in the output jitter of the fractional divider due to the much improved linearity.
• This plot is constructed from SPICE® simulation results.

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• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Pulse Circuits (AREA)
• Analogue/Digital Conversion (AREA)
• Filters That Use Time-Delay Elements (AREA)

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• 2011
  • 2011-06-03 US US13/153,190 patent/US8451042B2/en active Active
• 2012
  • 2012-06-04 CN CN201280037936.0A patent/CN103718460B/zh active Active
  • 2012-06-04 WO PCT/US2012/040718 patent/WO2012167239A2/en not_active Ceased
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