CN103718460B - 用于具有改善线性度的数字相位插值器的装置和系统 - Google Patents
用于具有改善线性度的数字相位插值器的装置和系统 Download PDFInfo
- Publication number
- CN103718460B CN103718460B CN201280037936.0A CN201280037936A CN103718460B CN 103718460 B CN103718460 B CN 103718460B CN 201280037936 A CN201280037936 A CN 201280037936A CN 103718460 B CN103718460 B CN 103718460B
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- CN
- China
- Prior art keywords
- switch
- driven
- coupled
- weighted
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Analogue/Digital Conversion (AREA)
- Filters That Use Time-Delay Elements (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/153,190 | 2011-06-03 | ||
| US13/153,190 US8451042B2 (en) | 2011-06-03 | 2011-06-03 | Apparatus and system of implementation of digital phase interpolator with improved linearity |
| PCT/US2012/040718 WO2012167239A2 (en) | 2011-06-03 | 2012-06-04 | Apparatus and systems digital phase interpolator with improved linearity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103718460A CN103718460A (zh) | 2014-04-09 |
| CN103718460B true CN103718460B (zh) | 2016-08-31 |
Family
ID=47260431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201280037936.0A Active CN103718460B (zh) | 2011-06-03 | 2012-06-04 | 用于具有改善线性度的数字相位插值器的装置和系统 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8451042B2 (enExample) |
| JP (1) | JP6141833B2 (enExample) |
| CN (1) | CN103718460B (enExample) |
| WO (1) | WO2012167239A2 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101326117B1 (ko) * | 2013-06-25 | 2013-11-06 | 홍익대학교 산학협력단 | 위상 반전 록킹 알고리즘을 이용한 디지털 지연 고정 루프 회로 및 제어방법 |
| US9407245B2 (en) * | 2014-06-30 | 2016-08-02 | Intel IP Corporation | System for digitally controlled edge interpolator linearization |
| CN106936437A (zh) * | 2015-12-31 | 2017-07-07 | 京微雅格(北京)科技有限公司 | 数模转换器、包括其的模数转换器及版图实现方法 |
| KR102671076B1 (ko) * | 2017-02-09 | 2024-05-30 | 에스케이하이닉스 주식회사 | 내부클럭생성회로 |
| US10483956B2 (en) | 2017-07-20 | 2019-11-19 | Rohm Co., Ltd. | Phase interpolator, timing generator, and semiconductor integrated circuit |
| JP6902952B2 (ja) * | 2017-07-20 | 2021-07-14 | ローム株式会社 | 位相補間器およびタイミング発生器、半導体集積回路 |
| US11387841B2 (en) | 2017-12-15 | 2022-07-12 | Intel Corporation | Apparatus and method for interpolating between a first signal and a second signal |
| CN108092649B (zh) * | 2018-01-03 | 2021-05-04 | 龙迅半导体(合肥)股份有限公司 | 一种相位插值器和相位插值器的控制方法 |
| US11088682B2 (en) * | 2018-12-14 | 2021-08-10 | Intel Corporation | High speed digital phase interpolator with duty cycle correction circuitry |
| US12176903B1 (en) * | 2023-07-12 | 2024-12-24 | Himax Technologies Limited | Duty cycle correction device for use in cascaded circuits and related large touch and display driver integration system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| US20030179027A1 (en) * | 2002-03-22 | 2003-09-25 | Kizer Jade M. | Locked loop with dual rail regulation |
| CN101030770A (zh) * | 2006-03-03 | 2007-09-05 | 恩益禧电子股份有限公司 | 频谱扩展时钟控制装置及频谱扩展时钟发生装置 |
| US20090179674A1 (en) * | 1999-11-26 | 2009-07-16 | Fujitsu Limited | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5512860A (en) * | 1994-12-02 | 1996-04-30 | Pmc-Sierra, Inc. | Clock recovery phase locked loop control using clock difference detection and forced low frequency startup |
| US5945862A (en) | 1997-07-31 | 1999-08-31 | Rambus Incorporated | Circuitry for the delay adjustment of a clock signal |
| CA2233831A1 (en) | 1998-03-31 | 1999-09-30 | Tom Riley | Digital-sigma fractional-n synthesizer |
| JP3789247B2 (ja) * | 1999-02-26 | 2006-06-21 | Necエレクトロニクス株式会社 | クロック周期検知回路 |
| US6114914A (en) | 1999-05-19 | 2000-09-05 | Cypress Semiconductor Corp. | Fractional synthesis scheme for generating periodic signals |
| JP3495311B2 (ja) * | 2000-03-24 | 2004-02-09 | Necエレクトロニクス株式会社 | クロック制御回路 |
| JP3498069B2 (ja) * | 2000-04-27 | 2004-02-16 | Necエレクトロニクス株式会社 | クロック制御回路および方法 |
| JP3450293B2 (ja) * | 2000-11-29 | 2003-09-22 | Necエレクトロニクス株式会社 | クロック制御回路及びクロック制御方法 |
| JP3636657B2 (ja) * | 2000-12-21 | 2005-04-06 | Necエレクトロニクス株式会社 | クロックアンドデータリカバリ回路とそのクロック制御方法 |
| KR100715845B1 (ko) | 2001-02-17 | 2007-05-10 | 삼성전자주식회사 | 위상혼합기 및 이를 이용한 다중위상 발생기 |
| US6952123B2 (en) * | 2002-03-22 | 2005-10-04 | Rambus Inc. | System with dual rail regulated locked loop |
| US7295077B2 (en) | 2003-05-02 | 2007-11-13 | Silicon Laboratories Inc. | Multi-frequency clock synthesizer |
| US20050093594A1 (en) | 2003-10-30 | 2005-05-05 | Infineon Technologies North America Corp. | Delay locked loop phase blender circuit |
| US7750695B2 (en) * | 2004-12-13 | 2010-07-06 | Mosaid Technologies Incorporated | Phase-locked loop circuitry using charge pumps with current mirror circuitry |
| US7596670B2 (en) | 2005-11-30 | 2009-09-29 | International Business Machines Corporation | Restricting access to improve data availability |
| US7417510B2 (en) | 2006-09-28 | 2008-08-26 | Silicon Laboratories Inc. | Direct digital interpolative synthesis |
| US7764134B2 (en) | 2007-06-14 | 2010-07-27 | Silicon Laboratories Inc. | Fractional divider |
| JP5451012B2 (ja) * | 2008-09-04 | 2014-03-26 | ピーエスフォー ルクスコ エスエイアールエル | Dll回路及びその制御方法 |
| US8258839B2 (en) * | 2010-10-15 | 2012-09-04 | Texas Instruments Incorporated | 1 to 2N-1 fractional divider circuit with fine fractional resolution |
-
2011
- 2011-06-03 US US13/153,190 patent/US8451042B2/en active Active
-
2012
- 2012-06-04 WO PCT/US2012/040718 patent/WO2012167239A2/en not_active Ceased
- 2012-06-04 JP JP2014513786A patent/JP6141833B2/ja active Active
- 2012-06-04 CN CN201280037936.0A patent/CN103718460B/zh active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6125157A (en) * | 1997-02-06 | 2000-09-26 | Rambus, Inc. | Delay-locked loop circuitry for clock delay adjustment |
| US20090179674A1 (en) * | 1999-11-26 | 2009-07-16 | Fujitsu Limited | Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
| US20030179027A1 (en) * | 2002-03-22 | 2003-09-25 | Kizer Jade M. | Locked loop with dual rail regulation |
| CN101030770A (zh) * | 2006-03-03 | 2007-09-05 | 恩益禧电子股份有限公司 | 频谱扩展时钟控制装置及频谱扩展时钟发生装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103718460A (zh) | 2014-04-09 |
| WO2012167239A2 (en) | 2012-12-06 |
| JP6141833B2 (ja) | 2017-06-07 |
| JP2014520436A (ja) | 2014-08-21 |
| WO2012167239A3 (en) | 2013-04-25 |
| US8451042B2 (en) | 2013-05-28 |
| US20120306552A1 (en) | 2012-12-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |