JP2013517711A5 - - Google Patents

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Publication number
JP2013517711A5
JP2013517711A5 JP2012549162A JP2012549162A JP2013517711A5 JP 2013517711 A5 JP2013517711 A5 JP 2013517711A5 JP 2012549162 A JP2012549162 A JP 2012549162A JP 2012549162 A JP2012549162 A JP 2012549162A JP 2013517711 A5 JP2013517711 A5 JP 2013517711A5
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JP
Japan
Prior art keywords
clock
signal
circuit
clock signal
pulse
Prior art date
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Granted
Application number
JP2012549162A
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English (en)
Japanese (ja)
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JP2013517711A (ja
JP5629329B2 (ja
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Publication date
Priority claimed from US12/690,064 external-priority patent/US8624647B2/en
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Publication of JP2013517711A publication Critical patent/JP2013517711A/ja
Publication of JP2013517711A5 publication Critical patent/JP2013517711A5/ja
Application granted granted Critical
Publication of JP5629329B2 publication Critical patent/JP5629329B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2012549162A 2010-01-19 2011-01-19 集積回路のメモリインターフェースのためのデューティサイクル補正器回路 Expired - Fee Related JP5629329B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/690,064 2010-01-19
US12/690,064 US8624647B2 (en) 2010-01-19 2010-01-19 Duty cycle correction circuit for memory interfaces in integrated circuits
PCT/US2011/021762 WO2011091073A2 (en) 2010-01-19 2011-01-19 Duty cycle correction circuit for memory interfaces in integrated circuits

Publications (3)

Publication Number Publication Date
JP2013517711A JP2013517711A (ja) 2013-05-16
JP2013517711A5 true JP2013517711A5 (enExample) 2014-01-09
JP5629329B2 JP5629329B2 (ja) 2014-11-19

Family

ID=44277186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012549162A Expired - Fee Related JP5629329B2 (ja) 2010-01-19 2011-01-19 集積回路のメモリインターフェースのためのデューティサイクル補正器回路

Country Status (5)

Country Link
US (1) US8624647B2 (enExample)
EP (1) EP2526552A4 (enExample)
JP (1) JP5629329B2 (enExample)
CN (1) CN102754161B (enExample)
WO (1) WO2011091073A2 (enExample)

Families Citing this family (18)

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Publication number Priority date Publication date Assignee Title
KR102000470B1 (ko) 2012-10-30 2019-07-16 삼성전자주식회사 듀티 정정 회로 및 이를 포함하는 시스템
US9607153B2 (en) 2013-03-13 2017-03-28 Qualcomm Incorporated Apparatus and method for detecting clock tampering
KR101576285B1 (ko) 2013-11-08 2015-12-10 건국대학교 산학협력단 펄스 발생 장치 및 회로
US9030244B1 (en) 2014-01-15 2015-05-12 Altera Corporation Clock duty cycle calibration circuitry
US9438208B2 (en) 2014-06-09 2016-09-06 Qualcomm Incorporated Wide-band duty cycle correction circuit
KR102315274B1 (ko) 2017-06-01 2021-10-20 삼성전자 주식회사 듀티 정정 회로를 포함하는 비휘발성 메모리 및 상기 비휘발성 메모리를 포함하는 스토리지 장치
US10482935B2 (en) 2017-06-01 2019-11-19 Samsung Electronics Co., Ltd. Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory
US10276229B2 (en) * 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing
US11226922B2 (en) * 2017-12-14 2022-01-18 Intel Corporation System, apparatus and method for controlling duty cycle of a clock signal for a multi-drop interconnect
EP3514956B1 (en) * 2018-01-19 2023-04-19 Socionext Inc. Clock distribution
CN109787588B (zh) * 2018-12-29 2023-03-14 西安紫光国芯半导体有限公司 一种ddr时钟路径及其低功耗的占空比校正电路
CN110492872B (zh) * 2019-09-12 2024-04-05 珠海微度芯创科技有限责任公司 数字占空比校正电路系统
JP7434770B2 (ja) * 2019-09-13 2024-02-21 株式会社リコー デューティー補正回路、受信回路およびデューティー補正方法
CN111562808B (zh) * 2020-06-22 2025-08-01 深圳比特微电子科技有限公司 时钟电路系统、计算芯片、算力板和数据处理设备
CN115118252A (zh) * 2021-03-19 2022-09-27 爱普存储技术(杭州)有限公司 占空比校正装置及占空比校正方法
KR102845124B1 (ko) * 2021-04-20 2025-08-12 삼성전자주식회사 직교 에러 정정 회로 및 이를 포함하는 반도체 메모리 장치
US11848668B2 (en) * 2022-03-11 2023-12-19 Microchip Technology Incorporated Apparatus and method for active inductor modulation
US12451873B2 (en) 2023-05-04 2025-10-21 Qualcomm Incorporated Quadrature duty cycle correction circuit

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JPH03258015A (ja) * 1990-03-07 1991-11-18 Mitsubishi Electric Corp 半導体集積回路
JPH0613857A (ja) * 1992-06-25 1994-01-21 Fujitsu Ltd ディレイ調整回路
JPH06188698A (ja) * 1992-12-16 1994-07-08 Sharp Corp 遅延回路およびこの遅延回路を用いた波形整形回路
JP3209720B2 (ja) * 1997-08-04 2001-09-17 松下電器産業株式会社 複数伝送線路間の遅延時間の調整装置及び調整方法
JPH11101390A (ja) * 1997-09-26 1999-04-13 Toyoda Mach Works Ltd 配 管
DE19821458C1 (de) * 1998-05-13 1999-11-18 Siemens Ag Schaltungsanordnung zur Erzeugung komplementärer Signale
JP3753925B2 (ja) * 2000-05-12 2006-03-08 株式会社ルネサステクノロジ 半導体集積回路
KR100346836B1 (ko) * 2000-06-07 2002-08-03 삼성전자 주식회사 듀티 사이클 보정 기능을 갖는 지연 동기 루프 회로 및지연 동기 방법
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KR100834400B1 (ko) * 2005-09-28 2008-06-04 주식회사 하이닉스반도체 Ｄｒａｍ의 동작 주파수를 높이기 위한 지연고정루프 및 그의 출력드라이버
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KR100837822B1 (ko) * 2007-01-10 2008-06-16 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
US7733143B2 (en) * 2007-12-21 2010-06-08 Agere Systems Inc. Duty cycle correction circuit for high-speed clock signals
KR101013444B1 (ko) * 2008-03-14 2011-02-14 주식회사 하이닉스반도체 듀티 사이클 보정 장치 및 이를 포함하는 반도체 집적 회로
US7940103B2 (en) * 2009-03-09 2011-05-10 Micron Technology, Inc. Duty cycle correction systems and methods
KR101030275B1 (ko) * 2009-10-30 2011-04-20 주식회사 하이닉스반도체 듀티 보정 회로 및 이를 포함하는 클럭 보정 회로

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