JP2013074351A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2013074351A5 JP2013074351A5 JP2011210078A JP2011210078A JP2013074351A5 JP 2013074351 A5 JP2013074351 A5 JP 2013074351A5 JP 2011210078 A JP2011210078 A JP 2011210078A JP 2011210078 A JP2011210078 A JP 2011210078A JP 2013074351 A5 JP2013074351 A5 JP 2013074351A5
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- transistors
- semiconductor device
- phase
- adjustment circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 claims 25
- 230000010363 phase shift Effects 0.000 claims 8
- 230000002194 synthesizing effect Effects 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011210078A JP2013074351A (ja) | 2011-09-27 | 2011-09-27 | 半導体装置 |
| US13/612,654 US8525563B2 (en) | 2011-09-27 | 2012-09-12 | Semiconductor device including DLL circuit having coarse adjustment unit and fine adjustment unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011210078A JP2013074351A (ja) | 2011-09-27 | 2011-09-27 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013074351A JP2013074351A (ja) | 2013-04-22 |
| JP2013074351A5 true JP2013074351A5 (enExample) | 2014-11-13 |
Family
ID=47910628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011210078A Abandoned JP2013074351A (ja) | 2011-09-27 | 2011-09-27 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8525563B2 (enExample) |
| JP (1) | JP2013074351A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180031859A (ko) * | 2016-09-19 | 2018-03-29 | 삼성전자주식회사 | 복수의 딜레이 라인을 포함하는 딜레이 고정 루프 |
| US11043941B2 (en) * | 2018-03-16 | 2021-06-22 | Micron Technology, Inc. | Apparatuses and methods for adjusting a phase mixer circuit |
| US11211936B1 (en) * | 2021-01-05 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delay lock loop circuits and methods for operating same |
| JP2022139835A (ja) * | 2021-03-12 | 2022-09-26 | ソニーセミコンダクタソリューションズ株式会社 | 光源駆動回路および測距装置 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100408727B1 (ko) * | 2001-12-28 | 2003-12-11 | 주식회사 하이닉스반도체 | 클럭 동기 장치 |
| KR100515071B1 (ko) * | 2003-04-29 | 2005-09-16 | 주식회사 하이닉스반도체 | 디엘엘 장치 |
| KR100605577B1 (ko) * | 2004-06-30 | 2006-07-31 | 주식회사 하이닉스반도체 | 레지스터 제어형 지연 고정 루프 및 그의 제어 방법 |
| KR100776906B1 (ko) * | 2006-02-16 | 2007-11-19 | 주식회사 하이닉스반도체 | 파워다운 모드 동안 주기적으로 락킹 동작을 실행하는기능을 가지는 dll 및 그 락킹 동작 방법 |
| US7671648B2 (en) * | 2006-10-27 | 2010-03-02 | Micron Technology, Inc. | System and method for an accuracy-enhanced DLL during a measure initialization mode |
| JP2009021706A (ja) | 2007-07-10 | 2009-01-29 | Elpida Memory Inc | Dll回路及びこれを用いた半導体記憶装置、並びに、データ処理システム |
| JP5579373B2 (ja) | 2008-05-22 | 2014-08-27 | ピーエスフォー ルクスコ エスエイアールエル | Dll回路 |
| US8653869B2 (en) * | 2011-10-20 | 2014-02-18 | Media Tek Singapore Pte. Ltd. | Segmented fractional-N PLL |
-
2011
- 2011-09-27 JP JP2011210078A patent/JP2013074351A/ja not_active Abandoned
-
2012
- 2012-09-12 US US13/612,654 patent/US8525563B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI742926B (zh) | 用於雙倍資料率裝置的占空比更正電路 | |
| CN105553446B (zh) | 信号产生系统和信号产生方法、信号组合模块 | |
| US20140062559A1 (en) | System and method of adjusting a clock signal | |
| JP2010246092A5 (enExample) | ||
| JP6783535B2 (ja) | クロック補正装置及びクロック補正方法 | |
| CN104899165B (zh) | 对电子装置执行存储接口控制的方法及其装置 | |
| US20170047917A1 (en) | Signal delay cells | |
| KR20150021364A (ko) | 위상 혼합 회로, 이를 포함하는 반도체 장치 및 반도체 시스템 | |
| JP2012256412A5 (enExample) | ||
| JP2013149310A5 (enExample) | ||
| JP2014146869A (ja) | 位相補間回路および受信回路 | |
| JP2013074351A5 (enExample) | ||
| WO2016089292A1 (en) | Power efficient high speed latch circuits and systems | |
| KR102211167B1 (ko) | 바디 바이어스 전압 생성기 및 이를 포함하는 시스템-온-칩 | |
| US9537475B1 (en) | Phase interpolator device using dynamic stop and phase code update and method therefor | |
| US9571077B1 (en) | Dynamic update technique for phase interpolator device and method therefor | |
| JP6845375B2 (ja) | 電位変換回路及び表示パネル | |
| JP6201401B2 (ja) | タイミング制御回路 | |
| US8466729B2 (en) | Delay cell and digitally controlled oscillator | |
| CN108988828B (zh) | 振荡器 | |
| JP6631531B2 (ja) | 送信装置、送信方法、および通信システム | |
| KR101998173B1 (ko) | 위상 분할 회로 | |
| JP2016127602A (ja) | クロック生成装置 | |
| JP2010283019A (ja) | クロック分配素子及びそれを用いたレイアウト設計方法 | |
| JP6289110B2 (ja) | 集積回路 |