CN102754161B - 用于集成电路中的存储器接口的占空比校正电路 - Google Patents

用于集成电路中的存储器接口的占空比校正电路 Download PDF

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Publication number
CN102754161B
CN102754161B CN201180006478.XA CN201180006478A CN102754161B CN 102754161 B CN102754161 B CN 102754161B CN 201180006478 A CN201180006478 A CN 201180006478A CN 102754161 B CN102754161 B CN 102754161B
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China
Prior art keywords
clock signal
signal
circuit
clock
coupled
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Expired - Fee Related
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CN201180006478.XA
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English (en)
Chinese (zh)
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CN102754161A (zh
Inventor
种燕
J·黄
P·纳加拉简
C·桑
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Altera Corp
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Altera Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
CN201180006478.XA 2010-01-19 2011-01-19 用于集成电路中的存储器接口的占空比校正电路 Expired - Fee Related CN102754161B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/690,064 2010-01-19
US12/690,064 US8624647B2 (en) 2010-01-19 2010-01-19 Duty cycle correction circuit for memory interfaces in integrated circuits
PCT/US2011/021762 WO2011091073A2 (en) 2010-01-19 2011-01-19 Duty cycle correction circuit for memory interfaces in integrated circuits

Publications (2)

Publication Number Publication Date
CN102754161A CN102754161A (zh) 2012-10-24
CN102754161B true CN102754161B (zh) 2016-01-20

Family

ID=44277186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180006478.XA Expired - Fee Related CN102754161B (zh) 2010-01-19 2011-01-19 用于集成电路中的存储器接口的占空比校正电路

Country Status (5)

Country Link
US (1) US8624647B2 (enExample)
EP (1) EP2526552A4 (enExample)
JP (1) JP5629329B2 (enExample)
CN (1) CN102754161B (enExample)
WO (1) WO2011091073A2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102000470B1 (ko) 2012-10-30 2019-07-16 삼성전자주식회사 듀티 정정 회로 및 이를 포함하는 시스템
US9607153B2 (en) 2013-03-13 2017-03-28 Qualcomm Incorporated Apparatus and method for detecting clock tampering
KR101576285B1 (ko) 2013-11-08 2015-12-10 건국대학교 산학협력단 펄스 발생 장치 및 회로
US9030244B1 (en) 2014-01-15 2015-05-12 Altera Corporation Clock duty cycle calibration circuitry
US9438208B2 (en) 2014-06-09 2016-09-06 Qualcomm Incorporated Wide-band duty cycle correction circuit
KR102315274B1 (ko) 2017-06-01 2021-10-20 삼성전자 주식회사 듀티 정정 회로를 포함하는 비휘발성 메모리 및 상기 비휘발성 메모리를 포함하는 스토리지 장치
US10482935B2 (en) 2017-06-01 2019-11-19 Samsung Electronics Co., Ltd. Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory
US10276229B2 (en) * 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing
US11226922B2 (en) * 2017-12-14 2022-01-18 Intel Corporation System, apparatus and method for controlling duty cycle of a clock signal for a multi-drop interconnect
EP3514956B1 (en) * 2018-01-19 2023-04-19 Socionext Inc. Clock distribution
CN109787588B (zh) * 2018-12-29 2023-03-14 西安紫光国芯半导体有限公司 一种ddr时钟路径及其低功耗的占空比校正电路
CN110492872B (zh) * 2019-09-12 2024-04-05 珠海微度芯创科技有限责任公司 数字占空比校正电路系统
JP7434770B2 (ja) * 2019-09-13 2024-02-21 株式会社リコー デューティー補正回路、受信回路およびデューティー補正方法
CN111562808B (zh) * 2020-06-22 2025-08-01 深圳比特微电子科技有限公司 时钟电路系统、计算芯片、算力板和数据处理设备
CN115118252A (zh) * 2021-03-19 2022-09-27 爱普存储技术(杭州)有限公司 占空比校正装置及占空比校正方法
KR102845124B1 (ko) * 2021-04-20 2025-08-12 삼성전자주식회사 직교 에러 정정 회로 및 이를 포함하는 반도체 메모리 장치
US11848668B2 (en) * 2022-03-11 2023-12-19 Microchip Technology Incorporated Apparatus and method for active inductor modulation
US12451873B2 (en) 2023-05-04 2025-10-21 Qualcomm Incorporated Quadrature duty cycle correction circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050286672A1 (en) * 2001-05-18 2005-12-29 Micron Technology, Inc. Phase splitter using digital delay locked loops
CN1945732A (zh) * 2005-09-28 2007-04-11 海力士半导体有限公司 用于高速半导体存储器装置的延迟锁定环
US20080164920A1 (en) * 2007-01-10 2008-07-10 Hynix Semiconductor Inc. DLL circuit and method of controlling the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57210718A (en) * 1981-06-10 1982-12-24 Nec Corp Signal change detecting circuit
JPH03258015A (ja) * 1990-03-07 1991-11-18 Mitsubishi Electric Corp 半導体集積回路
JPH0613857A (ja) * 1992-06-25 1994-01-21 Fujitsu Ltd ディレイ調整回路
JPH06188698A (ja) * 1992-12-16 1994-07-08 Sharp Corp 遅延回路およびこの遅延回路を用いた波形整形回路
JP3209720B2 (ja) * 1997-08-04 2001-09-17 松下電器産業株式会社 複数伝送線路間の遅延時間の調整装置及び調整方法
JPH11101390A (ja) * 1997-09-26 1999-04-13 Toyoda Mach Works Ltd 配 管
DE19821458C1 (de) * 1998-05-13 1999-11-18 Siemens Ag Schaltungsanordnung zur Erzeugung komplementärer Signale
JP3753925B2 (ja) * 2000-05-12 2006-03-08 株式会社ルネサステクノロジ 半導体集積回路
KR100346836B1 (ko) * 2000-06-07 2002-08-03 삼성전자 주식회사 듀티 사이클 보정 기능을 갖는 지연 동기 루프 회로 및지연 동기 방법
US7236028B1 (en) * 2005-07-22 2007-06-26 National Semiconductor Corporation Adaptive frequency variable delay-locked loop
KR100688591B1 (ko) * 2006-04-21 2007-03-02 삼성전자주식회사 위상 분할기
US7733143B2 (en) * 2007-12-21 2010-06-08 Agere Systems Inc. Duty cycle correction circuit for high-speed clock signals
KR101013444B1 (ko) * 2008-03-14 2011-02-14 주식회사 하이닉스반도체 듀티 사이클 보정 장치 및 이를 포함하는 반도체 집적 회로
US7940103B2 (en) * 2009-03-09 2011-05-10 Micron Technology, Inc. Duty cycle correction systems and methods
KR101030275B1 (ko) * 2009-10-30 2011-04-20 주식회사 하이닉스반도체 듀티 보정 회로 및 이를 포함하는 클럭 보정 회로

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050286672A1 (en) * 2001-05-18 2005-12-29 Micron Technology, Inc. Phase splitter using digital delay locked loops
CN1945732A (zh) * 2005-09-28 2007-04-11 海力士半导体有限公司 用于高速半导体存储器装置的延迟锁定环
US20080164920A1 (en) * 2007-01-10 2008-07-10 Hynix Semiconductor Inc. DLL circuit and method of controlling the same

Also Published As

Publication number Publication date
WO2011091073A3 (en) 2011-11-17
EP2526552A2 (en) 2012-11-28
CN102754161A (zh) 2012-10-24
EP2526552A4 (en) 2016-10-26
JP2013517711A (ja) 2013-05-16
WO2011091073A2 (en) 2011-07-28
JP5629329B2 (ja) 2014-11-19
US20110175657A1 (en) 2011-07-21
US8624647B2 (en) 2014-01-07

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