JP2013058603A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2013058603A JP2013058603A JP2011195980A JP2011195980A JP2013058603A JP 2013058603 A JP2013058603 A JP 2013058603A JP 2011195980 A JP2011195980 A JP 2011195980A JP 2011195980 A JP2011195980 A JP 2011195980A JP 2013058603 A JP2013058603 A JP 2013058603A
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Classifications
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- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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Abstract
【解決手段】実施の形態の半導体装置は、炭化珪素と、炭化珪素上に形成され、第1の層、第1の層よりも低い炭素比率を有する第2の層を備える金属シリサイドと、金属シリサイド上に形成される金属電極を備え、第2の層が第1の層上に形成され、第2の層が金属電極に接し、第2の層中の金属シリサイドの平均粒径が、第1の層中の金属シリサイドの平均粒径よりも大きい。
【選択図】図1
Description
本実施の形態の半導体装置は、炭化珪素と、炭化珪素上に形成され、第1の層、第1の層よりも低い炭素比率を有する第2の層を備える金属シリサイドと、金属シリサイド上に形成される金属電極を備える。そして、第2の層が第1の層上に形成され、第2の層が金属電極に接し、第2の層中の金属シリサイドの平均粒径が、第1の層中の金属シリサイドの平均粒径よりも大きい。
本実施の形態の半導体装置は、SiC基板表面に形成される第1のニッケルシリサイド領域ではなく、SiC基板裏面に形成される第2のニッケルシリサイド領域が、炭素高濃度層と炭素低濃度層を備えること以外は第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、第1のニッケルシリサイド領域に加えて、SiC基板裏面に形成される第2のニッケルシリサイド領域が、炭素高濃度層と炭素低濃度層を備えること以外は第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、ゲート電極が、多結晶シリコンとニッケルシリサイドの積層構造であること以外は、第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、ゲート電極が、すべてとニッケルシリサイドで形成される以外は第4の実施の形態と同様である。したがって、第4の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、DIMOSFETではなく、IGBT(Insulated Gate Bipolar Transistor)である点で第1の実施の形態と異なっている。ニッケルシリサイド領域の構造および製造方法の要部については、第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、PiN(p−intrinsic−n)ダイオードである点で第1の実施の形態と異なっている。ニッケルシリサイド領域の構造および製造方法の要部については、第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
本実施の形態の半導体装置は、MPS(Merged PiN and Shottky)ダイオードである点で第1の実施の形態と異なっている。ニッケルシリサイド領域の構造および製造方法の要部については、第1の実施の形態と同様である。したがって、第1の実施の形態と重複する内容については記載を省略する。
10a n+型SiC層(第1のn型炭化珪素層)
10b n−型SiC層(第2のn型炭化珪素層)
10c p+型SiC層(p型炭化珪素層)
12 p型SiC領域(第1のp型不純物領域)
14 n+型SiC領域(n型不純物領域)
16 p+型SiC領域(第2のp型不純物領域)
18 第1のニッケルシリサイド領域
18a 第1の層(炭素高濃度層)
18b 第2の層(炭素低濃度層)
20 ゲート絶縁膜
22 ゲート電極
28 第1の金属電極
30 第2のニッケルシリサイド領域
32 第2の金属電極
36 ニッケル膜
40 ダメージ層
50 第3の金属電極
100 DIMOSFET
200 DIMOSFET
300 DIMOSFET
400 DIMOSFET
500 DIMOSFET
600 IGBT
700 PiNダイオード
800 MPSダイオード
Claims (10)
- 炭化珪素と、
前記炭化珪素上に形成され、第1の層、前記第1の層よりも低い炭素比率を有する第2の層を備える金属シリサイドと、
前記金属シリサイド上に形成される金属電極とを備え、
前記第2の層が前記第1の層上に形成され、前記第2の層が前記金属電極に接し、前記第2の層中の金属シリサイドの平均粒径が、前記第1の層中の金属シリサイドの平均粒径よりも大きいことを特徴とする半導体装置。 - 前記金属シリサイドの膜厚が100nm以下であることを特徴とする請求項1記載の半導体装置。
- 前記第2の層中の炭素比率が20原子%未満、前記第1の層中の炭素比率が20原子%以上であることを特徴とする請求項1または請求項2記載の半導体装置。
- 前記金属シリサイドがニッケルシリサイドであることを特徴とする請求項1ないし請求項3いずれか一項記載の半導体装置。
- 炭化珪素の表面のシリコン(Si)−炭素(C)結合の少なくとも一部を破壊する工程と、
前記炭化珪素の表面上に金属膜を形成する工程と、
熱処理により、前記金属膜と前記炭化珪素を反応させ金属シリサイドを形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記シリコン(Si)−炭素(C)結合の少なくとも一部を破壊する工程は、イオン注入によることを特徴とする請求項5記載の半導体装置の製造方法。
- 前記シリコン(Si)−炭素(C)結合の少なくとも一部を破壊する工程は、前記炭化珪素を非晶質化しない限度で行うことを特徴とする請求項6記載の半導体装置の製造方法。
- 前記金属膜がニッケル膜であり、イオン注入される元素がGeであり、ドーズ量が1e13cm−2以上2e14cm−2以下であることを特徴とする請求項6または請求項7記載の半導体装置の製造方法。
- 第1のn型炭化珪素層と、前記第1のn型炭化珪素層よりもn型不物濃度の低い第2のn型炭化珪素層を有する半導体基板を準備する工程と、
前記第2のn型炭化珪素層に第1のp型不純物領域を形成する工程と、
前記第2のn型炭化珪素層にn型不純物領域を形成する工程と、
前記第1のp型不純物領域に接続され前記第1のp型不純物領域よりも深さが浅くp型不純物濃度の高い第2のp型不純物領域を形成する工程と、
前記第2のn型炭化珪素層、前記第1のp型不純物領域、前記n型不純物領域の表面にまたがるゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記n型不純物領域および前記第2のp型不純物領域の表面のシリコン(Si)−炭素(C)結合の少なくとも一部を破壊する工程と、
前記n型不純物領域および前記第2のp型不純物領域上に金属膜を形成する工程と、
熱処理により、前記金属膜と前記n型不純物領域および前記第2のp型不純物領域の炭化珪素を反応させ金属シリサイドを形成する工程と、
前記n型不純物領域上および前記第2のp型不純物領域上の前記金属シリサイド上に金属電極を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記ゲート電極がシリコンであって、
前記金属膜を形成する工程において、前記ゲート電極上にも前記金属膜を形成し、
前記金属シリサイドを形成する工程において、前記金属膜と前記ゲート電極のシリコンを反応させ前記金属シリサイドを形成することを特徴とする請求項9記載の半導体装置の製造方法。
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US20130062624A1 (en) | 2013-03-14 |
US8790983B2 (en) | 2014-07-29 |
US20140134817A1 (en) | 2014-05-15 |
US8669562B2 (en) | 2014-03-11 |
JP5728339B2 (ja) | 2015-06-03 |
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