CN104701372B - 横向扩散金属氧化物半导体器件及其制造方法 - Google Patents

横向扩散金属氧化物半导体器件及其制造方法 Download PDF

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CN104701372B
CN104701372B CN201310661189.4A CN201310661189A CN104701372B CN 104701372 B CN104701372 B CN 104701372B CN 201310661189 A CN201310661189 A CN 201310661189A CN 104701372 B CN104701372 B CN 104701372B
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CN104701372A (zh
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张广胜
张森
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CSMC Technologies Corp
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Abstract

本发明涉及一种LDMOS器件，包括衬底、衬底上的栅极、衬底内的埋层区和埋层区上的扩散层，埋层区包括第一埋层和第二埋层，第一埋层和第二埋层的掺杂杂质的导电类型相反，扩散层包括第一扩散区和第二扩散区，第一扩散区位于第一埋层上且与第一埋层邻接，第二扩散区位于第二埋层上且与第二埋层邻接，第一埋层与第一扩散区的掺杂杂质的导电类型相同，第二埋层与所述第二扩散区的掺杂杂质的导电类型相同。本发明还涉及一种LDMOS器件的制造方法。本发明器件在导通状态下的电流路径为第二扩散区的下部与第二埋层组成的区域，远离器件表面，从而可以增加器件的电流能力、减小导通电阻，并增加了器件的可靠性。

Description

横向扩散金属氧化物半导体器件及其制造方法
技术领域
本发明涉及半导体器件，特别是涉及一种LDMOS器件，还涉及一种LDMOS器件的制造方法。
背景技术
在传统的高压器件制备中，通常运用结深较深的阱或者低浓度的外延层来形成耐压层，其主要缺点在于：1、运用结深较深的阱来做为耐压区时，其杂质浓度最高的区域位于器件的表面，当表面注入相反类型杂质时，其最高杂质浓度区域被中和，导致器件的导通电阻增加；2、当使用外延层来作为耐压层时，其浓度分布为均匀的杂质分布，从而器件的导通电阻难以有效降低。
发明内容
基于此，有必要提供一种导通电阻较低的横向扩散金属氧化物半导体器件。
一种横向扩散金属氧化物半导体器件，包括衬底和衬底上的栅极，还包括衬底内的埋层区和埋层区上的扩散层，所述埋层区包括第一埋层和第二埋层，所述第一埋层和第二埋层的掺杂杂质的导电类型相反，所述扩散层包括第一扩散区和第二扩散区，所述第一扩散区位于第一埋层上且与所述第一埋层邻接，所述第二扩散区位于所述第二埋层上且与所述第二埋层邻接，所述第一埋层与第一扩散区的掺杂杂质的导电类型相同，所述第二埋层与所述第二扩散区的掺杂杂质的导电类型相同，所述栅极设于所述扩散层上。
在其中一个实施例中，所述扩散层还包括设于所述第二扩散区内的第三扩散区，所述第三扩散区与所述第二扩散区的掺杂杂质的导电类型相反，所述栅极的一端部分叠放于所述第三扩散区上。
在其中一个实施例中，还包括设于所述扩散层内的漏极引出区、源极引出区及衬底引出区，所述栅极的另一端靠近所述源极引出区。
在其中一个实施例中，所述源极引出区和衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述器件为常关型器件。
在其中一个实施例中，所述衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述源极引出区至少部分设于所述第二扩散区内，所述器件为常开型器件。
在其中一个实施例中，所述衬底是晶向为（100）的P型衬底。
本发明还提供一种横向扩散金属氧化物半导体器件的制造方法。
一种横向扩散金属氧化物半导体器件的制造方法，包括下列步骤：提供衬底；在衬底内形成埋层区；所述埋层区包括第一埋层和第二埋层，所述第一埋层和第二埋层的掺杂杂质的导电类型相反；在所述埋层区上形成硅区域；向所述硅区域内注入杂质离子并推结，形成第一扩散区和第二扩散区；所述第一扩散区位于第一埋层上且与所述第一埋层邻接，所述第二扩散区位于所述第二埋层上且与所述第二埋层邻接，所述第一埋层与第一扩散区的掺杂杂质的导电类型相同，所述第二埋层与所述第二扩散区的掺杂杂质的导电类型相同；在所述硅区域上形成栅氧层和栅极；形成源极引出区、漏极引出区和衬底引出区。
在其中一个实施例中，向所述硅区域内注入杂质离子并推结形成第一扩散区和第二扩散区的步骤之后、在所述硅区域上形成栅氧层和栅极的步骤之前，还包括在所述第二扩散区内形成第三扩散区的步骤；所述第三扩散区与所述第二扩散区的掺杂杂质的导电类型相反，所述栅极的一端部分叠放于所述第三扩散区上，另一端靠近所述源极引出区。
在其中一个实施例中，所述源极引出区和衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述器件为常关型器件。
在其中一个实施例中，所述衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述源极引出区至少部分设于所述第二扩散区内，所述器件为常开型器件。
上述横向扩散金属氧化物半导体器件，利用第二埋层与第二扩散区一起组成器件的高压耐压区，只需很短的高温推结时间，从而可以节约制造成本。经过高温推结后，第二埋层的杂质浓度很高，器件在导通状态下的电流路径为第二扩散区的下部与第二埋层组成的区域，远离器件表面，不易受器件表面的杂质浓度在后续工艺中改变的影响，从而可以增加器件的电流能力、减小导通电阻，并增加了器件的可靠性。
附图说明
图1为一种传统的横向扩散金属氧化物半导体（LDMOS）器件的结构示意图；
图2是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图；
图3a-图3e是一实施例中横向扩散金属氧化物半导体器件在制造过程中的剖面示意图；
图4是另一实施例中横向扩散金属氧化物半导体器件的剖面示意图。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1为一种传统的横向扩散金属氧化物半导体（LDMOS）器件的结构示意图。其中，第一扩散区11的结深很深，通常需要很长时间的高温推结过程，从而导致制造成本的增加。图中的箭头表示器件在正向开启时的电流通路，由于电流沟道中被区域12中和掉了一部分第一扩散区11的杂质浓度，从而电流能力会变小，导通电阻会增加。并且，电流的流动区域靠近器件表面，导致器件的可靠性较差。
图2是一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图，包括下列步骤：
S110，提供衬底。
在本实施例中，为了保证器件的纵向耐压，衬底采用掺杂浓度较低且晶向为（100）的P型衬底202（参照图3a）。
S120，在衬底内形成埋层区。
请参照图3a，埋层区包括第一埋层201和第二埋层203。其中，第一埋层201与第二埋层203的掺杂杂质的导电类型相反，第一埋层201与第二埋层203埋层可以紧贴在一起，也可以间隔一定的距离，通过习知的注入或其它工艺形成。
S130，在埋层区上形成硅区域。
请参照图3b，在本实施例中，硅区域204的掺杂杂质的导电类型与衬底202相同。在其它实施例中，硅区域204的掺杂杂质的导电类型也可以与衬底202相反。可以采用诸如淀积等工艺来形成硅区域204。
S140，向硅区域内注入杂质离子并推结，形成第一扩散区和第二扩散区。
请参照图3c，第一扩散区205和第二扩散区206在推结后分别与第一埋层201、第二埋层203直接对接。第一扩散区205与第二扩散区206的掺杂杂质的导电类型相反，第二扩散区206与第二埋层203的掺杂杂质的导电类型相同。第二埋层203与第二扩散区206一起组成器件的高压耐压区。
在本实施例中，第一埋层201与第二扩散区206有一个角相接。在其它实施例中，第二扩散区206也可以部分覆盖第一埋层201。请参照图3d，在本实施例中，步骤S140之后还包括在第二扩散区206内形成第三扩散区209的步骤。第三扩散区209的掺杂杂质的导电类型与第二扩散区206相反。设置第三扩散区209可以使第二扩散区206的掺杂浓度达到更高的水平，从而降低器件的导通电阻。
S150，在硅区域上形成栅氧层和栅极。
S160，形成源极引出区、漏极引出区和衬底引出区。
请参照图3e，在本实施例中，源极引出区212位于第一扩散区205内，漏极引出区210位于第二扩散区206内，衬底引出区213位于第一扩散区205内。栅极211的一端部分叠放于第三扩散区209上，另一端靠近源极引出区212。这种结构的器件为常关型器件。
请参照图4，在该实施例中，源极引出区212位于第二扩散区206内，漏极引出区210位于第二扩散区206内，衬底引出区213位于第一扩散区205内。这种结构的器件为常开型器件。
上述LDMOS器件，利用第二埋层203与第二扩散区206一起组成器件的高压耐压区，只需很短的高温推结时间，从而可以节约制造成本。经过高温推结后，第二埋层203的杂质浓度很高，器件在导通状态下的电流路径为第二扩散区206的下部分与第二埋层203组成的区域，远离器件表面，不易受器件表面的杂质浓度在后续工艺中被改变的影响，从而可以增加器件的电流能力、减小导通电阻，并增加了器件的可靠性。
图3e所示的横向扩散金属氧化物半导体器件，包括衬底202、衬底202上的栅极211，其中衬底202内设埋层区及扩散层。埋层区包括第一埋层201和第二埋层203，第一埋层201和第二埋层203的掺杂杂质的导电类型相反。扩散层包括第一扩散区205和第二扩散区206，第一扩散区205位于第一埋层201上且与第一埋层201邻接，第二扩散区206位于第二埋层203上且与第二埋层203邻接。第一埋层201与第一扩散区205的掺杂杂质的导电类型相同，第二埋层203与第二扩散区206的掺杂杂质的导电类型相同。第一扩散区205内设有源极引出区212、衬底引出区213，第二扩散区206内设有漏极引出区210。栅极211设于扩散层上，一端部分叠放于第三扩散区209上，另一端靠近源极引出区212。
在本实施例中，衬底202采用晶向为（100）的P型衬底。
在本实施例中，第二扩散区内206内还设有第三扩散区209，第三扩散区209与第二扩散区206的掺杂杂质的导电类型相反。
在本实施例中，第一埋层201与第二扩散区206有一个角相接，源极引出区212设于第一扩散区205内，这种结构的器件为常关型器件。在图4所示实施例中，第二扩散区206部分覆盖第一埋层201，源极引出区212设于第二扩散区206内，这种结构的器件为常关型器件。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (7)

1.一种横向扩散金属氧化物半导体器件，包括衬底和衬底上的栅极，其特征在于，还包括衬底内的埋层区和埋层区上的扩散层，所述埋层区包括第一埋层和第二埋层，所述第一埋层和第二埋层的掺杂杂质的导电类型相反，所述扩散层包括第一扩散区和第二扩散区，所述第一扩散区位于第一埋层上且与所述第一埋层邻接，所述第二扩散区位于所述第二埋层上且与所述第二埋层邻接，所述第一埋层与第一扩散区的掺杂杂质的导电类型相同，所述第二埋层与所述第二扩散区的掺杂杂质的导电类型相同，所述栅极设于所述扩散层上；所述扩散层还包括设于所述第二扩散区内的第三扩散区，所述第三扩散区与所述第二扩散区的掺杂杂质的导电类型相反，所述栅极的一端部分叠放于所述第三扩散区上；所述横向扩散金属氧化物半导体器件还包括设于所述扩散层内的漏极引出区、源极引出区及衬底引出区，所述栅极的另一端靠近所述源极引出区。
2.根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述源极引出区和衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述器件为常关型器件。
3.根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述源极引出区至少部分设于所述第二扩散区内，所述器件为常开型器件。
4.根据权利要求1所述的横向扩散金属氧化物半导体器件，其特征在于，所述衬底是晶向为(100)的P型衬底。
5.一种横向扩散金属氧化物半导体器件的制造方法，包括下列步骤：
提供衬底；
在衬底内形成埋层区；所述埋层区包括第一埋层和第二埋层，所述第一埋层和第二埋层的掺杂杂质的导电类型相反；
在所述埋层区上形成硅区域；
向所述硅区域内注入杂质离子并推结，形成第一扩散区和第二扩散区；所述第一扩散区位于第一埋层上且与所述第一埋层邻接，所述第二扩散区位于所述第二埋层上且与所述第二埋层邻接，所述第一埋层与第一扩散区的掺杂杂质的导电类型相同，所述第二埋层与所述第二扩散区的掺杂杂质的导电类型相同；
在所述第二扩散区内形成第三扩散区；所述第三扩散区与所述第二扩散区的掺杂杂质的导电类型相反；
在所述硅区域上形成栅氧层和栅极；所述栅极的一端部分叠放于所述第三扩散区上，另一端靠近源极引出区；
形成源极引出区、漏极引出区和衬底引出区。
6.根据权利要求5所述的横向扩散金属氧化物半导体器件的制造方法，其特征在于，所述源极引出区和衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述器件为常关型器件。
7.根据权利要求5所述的横向扩散金属氧化物半导体器件的制造方法，其特征在于，所述衬底引出区设于所述第一扩散区内，所述漏极引出区设于所述第二扩散区内，所述源极引出区至少部分设于所述第二扩散区内，所述器件为常开型器件。
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